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arch-gcn3: make read2st64_b32 write proper registers

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Per the GCN3 ISA, read2st64_b32 writes to consecutive registers

Change-Id: Ibc1672584a72cf7de12e06068a03fe304b34dce2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32236
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Kyle Roarty
2020-08-05 14:08:31 -05:00
parent c07a3548c4
commit d542dc838e
1 changed files with 1 additions and 1 deletions
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2
src/arch/gcn3/insts/instructions.cc
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@@ -32206,7 +32206,7 @@ namespace Gcn3ISA
Inst_DS__DS_READ2ST64_B32::completeAcc(GPUDynInstPtr gpuDynInst)
{
VecOperandU32 vdst0(gpuDynInst, extData.VDST);
VecOperandU32 vdst1(gpuDynInst, extData.VDST + 2);
VecOperandU32 vdst1(gpuDynInst, extData.VDST + 1);
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {