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stdlib: Add a new private_l1_private_l2_walk_cache_hierarchy.py module

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From [1] The PrivateL1PrivateL2Cache hierarchy has been amended
with an MMUCache, which is basically a small cache in front
of the page table walker. Not every ISA makes use of it.

Arm for example already implements caching of page table
walks, via the partial_levels parameter in the ArmTLB.

With this patch we define a new module which explicitly makes
use of the WalkCache. Configurations that do not require
another cache in the first level of the memsys (for the ptw)
can use the PrivateL1PrivateL2CacheHierarchy

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/49364

Change-Id: I17f7e68940ee947ca5b30e6ab3a01dafeed0f338
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Giacomo Travaglini
2024-03-14 14:42:25 +00:00
parent 0ec8cf8d05
commit d32a438913
3 changed files with 103 additions and 16 deletions
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3
src/python/SConscript
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@@ -91,6 +91,9 @@ PySource('gem5.components.cachehierarchies.classic',
PySource('gem5.components.cachehierarchies.classic',
'gem5/components/cachehierarchies/classic/'
'private_l1_private_l2_cache_hierarchy.py')
PySource('gem5.components.cachehierarchies.classic',
'gem5/components/cachehierarchies/classic/'
'private_l1_private_l2_walk_cache_hierarchy.py')
PySource('gem5.components.cachehierarchies.classic',
'gem5/components/cachehierarchies/classic/'
'private_l1_shared_l2_cache_hierarchy.py')