diff --git a/src/python/SConscript b/src/python/SConscript index ec3b03cdcf..49bc616ae2 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -91,6 +91,9 @@ PySource('gem5.components.cachehierarchies.classic', PySource('gem5.components.cachehierarchies.classic', 'gem5/components/cachehierarchies/classic/' 'private_l1_private_l2_cache_hierarchy.py') +PySource('gem5.components.cachehierarchies.classic', + 'gem5/components/cachehierarchies/classic/' + 'private_l1_private_l2_walk_cache_hierarchy.py') PySource('gem5.components.cachehierarchies.classic', 'gem5/components/cachehierarchies/classic/' 'private_l1_shared_l2_cache_hierarchy.py') diff --git a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py index d1d43ec0c8..e0f918a7d5 100644 --- a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py +++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py @@ -1,3 +1,15 @@ +# Copyright (c) 2024 Arm Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2021 The Regents of the University of California # All rights reserved. # @@ -26,6 +38,7 @@ from m5.objects import ( BadAddr, + BaseCPU, BaseXBar, Cache, L2XBar, @@ -42,7 +55,6 @@ from .abstract_classic_cache_hierarchy import AbstractClassicCacheHierarchy from .caches.l1dcache import L1DCache from .caches.l1icache import L1ICache from .caches.l2cache import L2Cache -from .caches.mmu_cache import MMUCache class PrivateL1PrivateL2CacheHierarchy( @@ -130,16 +142,6 @@ class PrivateL1PrivateL2CacheHierarchy( L2Cache(size=self._l2_size) for i in range(board.get_processor().get_num_cores()) ] - # ITLB Page walk caches - self.iptw_caches = [ - MMUCache(size="8KiB") - for _ in range(board.get_processor().get_num_cores()) - ] - # DTLB Page walk caches - self.dptw_caches = [ - MMUCache(size="8KiB") - for _ in range(board.get_processor().get_num_cores()) - ] if board.has_coherent_io(): self._setup_io_cache(board) @@ -150,16 +152,12 @@ class PrivateL1PrivateL2CacheHierarchy( self.l1icaches[i].mem_side = self.l2buses[i].cpu_side_ports self.l1dcaches[i].mem_side = self.l2buses[i].cpu_side_ports - self.iptw_caches[i].mem_side = self.l2buses[i].cpu_side_ports - self.dptw_caches[i].mem_side = self.l2buses[i].cpu_side_ports self.l2buses[i].mem_side_ports = self.l2caches[i].cpu_side self.membus.cpu_side_ports = self.l2caches[i].mem_side - cpu.connect_walker_ports( - self.iptw_caches[i].cpu_side, self.dptw_caches[i].cpu_side - ) + self._connect_table_walker(i, cpu) if board.get_processor().get_isa() == ISA.X86: int_req_port = self.membus.mem_side_ports @@ -168,6 +166,11 @@ class PrivateL1PrivateL2CacheHierarchy( else: cpu.connect_interrupt() + def _connect_table_walker(self, cpu_id: int, cpu: BaseCPU) -> None: + cpu.connect_walker_ports( + self.membus.cpu_side_ports, self.membus.cpu_side_ports + ) + def _setup_io_cache(self, board: AbstractBoard) -> None: """Create a cache for coherent I/O connections""" self.iocache = Cache( diff --git a/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_walk_cache_hierarchy.py b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_walk_cache_hierarchy.py new file mode 100644 index 0000000000..3f5999f0f5 --- /dev/null +++ b/src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_walk_cache_hierarchy.py @@ -0,0 +1,81 @@ +# Copyright (c) 2024 Arm Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Copyright (c) 2021 The Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects import BaseCPU + +from ....utils.override import * +from ...boards.abstract_board import AbstractBoard +from .caches.mmu_cache import MMUCache +from .private_l1_private_l2_cache_hierarchy import ( + PrivateL1PrivateL2CacheHierarchy, +) + + +class PrivateL1PrivateL2WalkCacheHierarchy(PrivateL1PrivateL2CacheHierarchy): + """ + A cache setup where each core has a private L1 Data and Instruction Cache, + and a private L2 cache and a Walk Cache for the Table Walker + """ + + def __init__(self, *args, **kwargs) -> None: + PrivateL1PrivateL2CacheHierarchy.__init__(self, *args, **kwargs) + + @overrides(PrivateL1PrivateL2CacheHierarchy) + def incorporate_cache(self, board: AbstractBoard) -> None: + # ITLB Page walk caches + self.iptw_caches = [ + MMUCache(size="8KiB") + for _ in range(board.get_processor().get_num_cores()) + ] + # DTLB Page walk caches + self.dptw_caches = [ + MMUCache(size="8KiB") + for _ in range(board.get_processor().get_num_cores()) + ] + + super().incorporate_cache(board) + + for i, cpu in enumerate(board.get_processor().get_cores()): + self.iptw_caches[i].mem_side = self.l2buses[i].cpu_side_ports + self.dptw_caches[i].mem_side = self.l2buses[i].cpu_side_ports + + def _connect_table_walker(self, cpu_id: int, cpu: BaseCPU) -> None: + cpu.connect_walker_ports( + self.iptw_caches[cpu_id].cpu_side, + self.dptw_caches[cpu_id].cpu_side, + )