derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-arm: Implement TLBI Shareable as a DVM op

Browse Source 
JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: Ie0a374abce41997af600773cc270a47cdf2c1338
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56606
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2021-10-25 15:18:30 +01:00
parent dbc91308c7
commit d2910d68c1
2 changed files with 20 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/arch/arm/isa/formats/aarch64.isa
View File

@@ -1,4 +1,4 @@
// Copyright (c) 2011-2021 Arm Limited
// Copyright (c) 2011-2022 Arm Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -37,7 +37,7 @@ output header {{
namespace Aarch64
{
StaticInstPtr decodeDataProcImm(ExtMachInst machInst);
StaticInstPtr decodeBranchExcSys(ExtMachInst machInst);
StaticInstPtr decodeBranchExcSys(const Decoder &dec, ExtMachInst machInst);
StaticInstPtr decodeLoadsStores(ExtMachInst machInst);
StaticInstPtr decodeDataProcReg(ExtMachInst machInst);
@@ -207,7 +207,7 @@ output decoder {{
namespace Aarch64
{
StaticInstPtr
decodeBranchExcSys(ExtMachInst machInst)
decodeBranchExcSys(const Decoder &dec, ExtMachInst machInst)
{
switch (bits(machInst, 30, 29)) {
case 0x0:
@@ -551,7 +551,7 @@ namespace Aarch64
case MISCREG_TLBI_IPAS2E1IS_Xt:
case MISCREG_TLBI_IPAS2LE1IS_Xt:
return new Tlbi64ShareableHub(
machInst, miscReg, rt, iss);
machInst, miscReg, rt, iss, dec.dvmEnabled);
default:
return new Msr64(machInst, miscReg, rt, iss);
}
@@ -3106,7 +3106,7 @@ def format Aarch64() {{
return decodeDataProcImm(machInst);
else
// bit 28:26=101
return decodeBranchExcSys(machInst);
return decodeBranchExcSys(*this, machInst);
} else if (bits(machInst, 25) == 0) {
// bit 27=1, 25=0
return decodeLoadsStores(machInst);

18
src/arch/arm/isa/insts/data64.isa
View File

@@ -378,12 +378,24 @@ let {{
decoder_output += MiscRegRegOp64Constructor.subst(msrTlbiIop)
exec_output += BasicExecute.subst(msrTlbiIop)
dvmCode = '''
if (dvmEnabled) {
Request::Flags memAccessFlags =
Request::STRICT_ORDER | Request::TLBI;
fault = xc->initiateSpecialMemCmd(memAccessFlags);
PendingDvm = true;
}
'''
msrTlbiSIop = ArmInstObjParams("msr", "Tlbi64ShareableHub", "TlbiOp64",
tlbiCode,
{ "code" : tlbiCode, "dvm_code" : dvmCode },
["IsSerializeAfter", "IsNonSpeculative"])
header_output += MiscRegRegOp64Declare.subst(msrTlbiSIop)
decoder_output += MiscRegRegOp64Constructor.subst(msrTlbiSIop)
header_output += DvmTlbiDeclare.subst(msrTlbiSIop)
decoder_output += DvmTlbiConstructor.subst(msrTlbiSIop)
exec_output += BasicExecute.subst(msrTlbiSIop)
exec_output += DvmInitiateAcc.subst(msrTlbiSIop)
exec_output += DvmCompleteAcc.subst(msrTlbiSIop)
buildDataXRegInst("msrNZCV", 1, '''
CPSR cpsr = XOp1;