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cpu: Merge TimingExprSrcReg and TimingExprReadIntReg.

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Make it possible to read any type of reg, assuming it fits in a RegVal.
This avoids assuming building in a dependency on the readIntReg
accessor.

It also avoids setting up a situation where the API could at least
theoretically base the timing expression on the value of *any* int reg,
even ones the instruction does not interact with. The ...ReadIntReg
expression was only ever used with the result of the ...SrcReg
expression, and in my opinion, that's realy the only way it makes sense
to use it. It doesn't seem useful to split that operation into two
parts.

If it actually does make sense (although I doubt this), these operations
can't really be generalized easily since the TimingExpr... classes all
expect to pass around uint64_ts, and a RegId, the *real* value of a
SrcReg index which does not assume a register type, would not fit in
that in the general case.

Change-Id: I253a0a058dc078deeb28ef0babead4c8ffc3b792
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49776
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
This commit is contained in:
Gabe Black
2021-08-29 00:30:10 -07:00
parent 590719a383
commit d222f4095b
5 changed files with 12 additions and 53 deletions
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21
configs/common/cores/arm/HPI.py
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@@ -144,20 +144,13 @@ def if_expr(cond, true_expr, false_expr):
return ret
return body
def src(index):
def src_reg(index):
def body(env):
ret = TimingExprSrcReg()
ret.index = index
return ret
return body
def int_reg(reg):
def body(env):
ret = TimingExprReadIntReg()
ret.reg = reg(env)
return ret
return body
def let(bindings, expr):
def body(env):
ret = TimingExprLet()
@@ -488,8 +481,8 @@ class HPI_SBFX_UBFX_A1(MinorFUTiming):
### SDIV
sdiv_lat_expr = expr_top(let([
('left', un('SignExtend32To64', int_reg(src(4)))),
('right', un('SignExtend32To64', int_reg(src(3)))),
('left', un('SignExtend32To64', src_reg(4))),
('right', un('SignExtend32To64', src_reg(3))),
('either_signed', bin('Or',
bin('SLessThan', ref('left'), literal(0)),
bin('SLessThan', ref('right'), literal(0)))),
@@ -511,8 +504,8 @@ sdiv_lat_expr = expr_top(let([
))
sdiv_lat_expr64 = expr_top(let([
('left', un('SignExtend32To64', int_reg(src(0)))),
('right', un('SignExtend32To64', int_reg(src(1)))),
('left', un('SignExtend32To64', src_reg(0))),
('right', un('SignExtend32To64', src_reg(1))),
('either_signed', bin('Or',
bin('SLessThan', ref('left'), literal(0)),
bin('SLessThan', ref('right'), literal(0)))),
@@ -773,8 +766,8 @@ class HPI_UDIV_T1(MinorFUTiming):
mask, match = t32_opcode('1111_1011_1011_xxxx__xxxx_xxxx_1111_xxxx')
udiv_lat_expr = expr_top(let([
('left', int_reg(src(4))),
('right', int_reg(src(3))),
('left', src_reg(4)),
('right', src_reg(3)),
('left_size', un('SizeInBits', ref('left'))),
('right_size', un('SizeInBits',
bin('UDiv', ref('right'), literal(2)))),