diff --git a/configs/common/cores/arm/HPI.py b/configs/common/cores/arm/HPI.py
index 3a11133a5b..8f3a11373a 100644
--- a/configs/common/cores/arm/HPI.py
+++ b/configs/common/cores/arm/HPI.py
@@ -144,20 +144,13 @@ def if_expr(cond, true_expr, false_expr):
         return ret
     return body
 
-def src(index):
+def src_reg(index):
     def body(env):
         ret = TimingExprSrcReg()
         ret.index = index
         return ret
     return body
 
-def int_reg(reg):
-    def body(env):
-        ret = TimingExprReadIntReg()
-        ret.reg = reg(env)
-        return ret
-    return body
-
 def let(bindings, expr):
     def body(env):
         ret = TimingExprLet()
@@ -488,8 +481,8 @@ class HPI_SBFX_UBFX_A1(MinorFUTiming):
 ### SDIV
 
 sdiv_lat_expr = expr_top(let([
-    ('left', un('SignExtend32To64', int_reg(src(4)))),
-    ('right', un('SignExtend32To64', int_reg(src(3)))),
+    ('left', un('SignExtend32To64', src_reg(4))),
+    ('right', un('SignExtend32To64', src_reg(3))),
     ('either_signed', bin('Or',
         bin('SLessThan', ref('left'), literal(0)),
         bin('SLessThan', ref('right'), literal(0)))),
@@ -511,8 +504,8 @@ sdiv_lat_expr = expr_top(let([
     ))
 
 sdiv_lat_expr64 = expr_top(let([
-    ('left', un('SignExtend32To64', int_reg(src(0)))),
-    ('right', un('SignExtend32To64', int_reg(src(1)))),
+    ('left', un('SignExtend32To64', src_reg(0))),
+    ('right', un('SignExtend32To64', src_reg(1))),
     ('either_signed', bin('Or',
         bin('SLessThan', ref('left'), literal(0)),
         bin('SLessThan', ref('right'), literal(0)))),
@@ -773,8 +766,8 @@ class HPI_UDIV_T1(MinorFUTiming):
     mask, match = t32_opcode('1111_1011_1011_xxxx__xxxx_xxxx_1111_xxxx')
 
 udiv_lat_expr = expr_top(let([
-    ('left', int_reg(src(4))),
-    ('right', int_reg(src(3))),
+    ('left', src_reg(4)),
+    ('right', src_reg(3)),
     ('left_size', un('SizeInBits', ref('left'))),
     ('right_size', un('SizeInBits',
         bin('UDiv', ref('right'), literal(2)))),
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index fad601eea2..446dc94d3f 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -98,9 +98,8 @@ SimObject('BaseCPU.py', sim_objects=['BaseCPU'])
 SimObject('CPUTracers.py', sim_objects=[
     'ExeTracer', 'IntelTrace', 'NativeTrace'])
 SimObject('TimingExpr.py', sim_objects=[
-    'TimingExpr', 'TimingExprLiteral', 'TimingExprSrcReg',
-    'TimingExprReadIntReg', 'TimingExprLet', 'TimingExprRef', 'TimingExprUn',
-    'TimingExprBin', 'TimingExprIf'],
+    'TimingExpr', 'TimingExprLiteral', 'TimingExprSrcReg', 'TimingExprLet',
+    'TimingExprRef', 'TimingExprUn', 'TimingExprBin', 'TimingExprIf'],
     enums=['TimingExprOp'])
 
 Source('activity.cc')
diff --git a/src/cpu/TimingExpr.py b/src/cpu/TimingExpr.py
index 9c45097abd..2a6c49a52e 100644
--- a/src/cpu/TimingExpr.py
+++ b/src/cpu/TimingExpr.py
@@ -66,30 +66,17 @@ class TimingExpr0(TimingExprLiteral):
     value = 0
 
 class TimingExprSrcReg(TimingExpr):
-    """Find the source register number from the current inst"""
+    """Read a source register from the current inst"""
     type = 'TimingExprSrcReg'
     cxx_header = 'cpu/timing_expr.hh'
     cxx_class = 'gem5::TimingExprSrcReg'
 
-    # index = Param.Unsigned("index into inst src regs")
-    index = Param.Unsigned("index into inst src regs")
+    index = Param.Unsigned("index into inst src regs of the reg to read")
 
     def set_params(self, index):
         self.index = index
         return self
 
-class TimingExprReadIntReg(TimingExpr):
-    """Read an architectural register"""
-    type = 'TimingExprReadIntReg'
-    cxx_header = 'cpu/timing_expr.hh'
-    cxx_class = 'gem5::TimingExprReadIntReg'
-
-    reg = Param.TimingExpr("register raw index to read")
-
-    def set_params(self, reg):
-        self.reg = reg
-        return self
-
 class TimingExprLet(TimingExpr):
     """Block of declarations"""
     type = 'TimingExprLet'
diff --git a/src/cpu/timing_expr.cc b/src/cpu/timing_expr.cc
index 41868a5ac9..d1f8186f88 100644
--- a/src/cpu/timing_expr.cc
+++ b/src/cpu/timing_expr.cc
@@ -59,13 +59,7 @@ TimingExprEvalContext::TimingExprEvalContext(const StaticInstPtr &inst_,
 uint64_t
 TimingExprSrcReg::eval(TimingExprEvalContext &context)
 {
-    return context.inst->srcRegIdx(index).index();
-}
-
-uint64_t
-TimingExprReadIntReg::eval(TimingExprEvalContext &context)
-{
-    return context.thread->readIntReg(reg->eval(context));
+    return context.thread->getReg(context.inst->srcRegIdx(index));
 }
 
 uint64_t
diff --git a/src/cpu/timing_expr.hh b/src/cpu/timing_expr.hh
index 170364e281..76212bdf49 100644
--- a/src/cpu/timing_expr.hh
+++ b/src/cpu/timing_expr.hh
@@ -55,7 +55,6 @@
 #include "params/TimingExprIf.hh"
 #include "params/TimingExprLet.hh"
 #include "params/TimingExprLiteral.hh"
-#include "params/TimingExprReadIntReg.hh"
 #include "params/TimingExprRef.hh"
 #include "params/TimingExprSrcReg.hh"
 #include "params/TimingExprUn.hh"
@@ -124,19 +123,6 @@ class TimingExprSrcReg : public TimingExpr
     uint64_t eval(TimingExprEvalContext &context);
 };
 
-class TimingExprReadIntReg : public TimingExpr
-{
-  public:
-    TimingExpr *reg;
-
-    TimingExprReadIntReg(const TimingExprReadIntRegParams &params) :
-        TimingExpr(params),
-        reg(params.reg)
-    { }
-
-    uint64_t eval(TimingExprEvalContext &context);
-};
-
 class TimingExprLet : public TimingExpr
 {
   public: