ARM: Add in more bits for the mon mode.

src/arch/arm/isa.hh

@@ -63,6 +63,9 @@ namespace ArmISA
               case MODE_SVC:
                 intRegMap = IntRegSvcMap;
                 break;
+              case MODE_MON:
+                intRegMap = IntRegMonMap;
+                break;
               case MODE_ABORT:
                 intRegMap = IntRegAbtMap;
                 break;

src/arch/arm/miscregs.hh

@@ -59,6 +59,7 @@ namespace ArmISA
         MISCREG_SPSR_FIQ,
         MISCREG_SPSR_IRQ,
         MISCREG_SPSR_SVC,
+        MISCREG_SPSR_MON,
         MISCREG_SPSR_UND,
         MISCREG_SPSR_ABT,
         MISCREG_FPSR,

src/arch/arm/types.hh

@@ -156,6 +156,7 @@ namespace ArmISA
         MODE_FIQ = 17,
         MODE_IRQ = 18,
         MODE_SVC = 19,
+        MODE_MON = 22,
         MODE_ABORT = 23,
         MODE_UNDEFINED = 27,
         MODE_SYSTEM = 31