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misc: Run pre-commit run --all-files

Browse Source 
This ensures `isort` is applied to all files in the repo.

Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9
This commit is contained in:
Bobby R. Bruce
2023-11-29 22:06:41 -08:00
parent 7d67109ca2
commit d11c40dcac
681 changed files with 3729 additions and 2487 deletions
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4
tests/gem5/__init__.py
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@@ -24,8 +24,8 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import testlib.suite
import testlib.fixture
import testlib.suite
from .suite import *
from .fixture import *
from .suite import *

33
tests/gem5/arm_boot_tests/configs/arm_boot_exit_run.py
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@@ -33,24 +33,27 @@ Characteristics
* Runs exclusively on the ARM ISA with the classic caches
"""
from gem5.isas import ISA
from m5.objects import ArmDefaultRelease
from gem5.utils.requires import requires
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
from m5.objects import VExpress_GEM5_Foundation
from gem5.coherence_protocol import CoherenceProtocol
from gem5.components.boards.arm_board import ArmBoard
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.cpu_types import (
get_cpu_types_str_set,
get_cpu_type_from_str,
CPUTypes,
)
import argparse
import importlib
from m5.objects import (
ArmDefaultRelease,
VExpress_GEM5_Foundation,
)
from gem5.coherence_protocol import CoherenceProtocol
from gem5.components.boards.arm_board import ArmBoard
from gem5.components.processors.cpu_types import (
CPUTypes,
get_cpu_type_from_str,
get_cpu_types_str_set,
)
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
parser = argparse.ArgumentParser(
description="A script to run the ARM boot exit tests."
)

1
tests/gem5/arm_boot_tests/test_linux_boot.py
View File

@@ -25,7 +25,6 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import re
from typing import Optional
from testlib import *

18
tests/gem5/asmtest/configs/riscv_asmtest.py
View File

@@ -31,19 +31,19 @@ The system has no cache heirarchy and is as "bare-bones" as you can get in
gem5 while still being functinal.
"""
from gem5.resources.resource import obtain_resource
from gem5.components.processors.cpu_types import (
get_cpu_types_str_set,
get_cpu_type_from_str,
)
from gem5.components.memory import SingleChannelDDR3_1600
import argparse
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import (
get_cpu_type_from_str,
get_cpu_types_str_set,
)
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.simulate.simulator import Simulator
from gem5.isas import ISA
import argparse
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
parser = argparse.ArgumentParser(
description="A gem5 script for testing RISC-V instructions"

17
tests/gem5/checkpoint_tests/configs/arm-hello-restore-checkpoint.py
View File

@@ -34,19 +34,20 @@ runs the rest of "arm-hello64-static" binary simulation.
This configuration serves as a test of restoring a checkpoint with ARM ISA.
"""
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import obtain_resource, CheckpointResource
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
PrivateL1PrivateL2CacheHierarchy,
)
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.simulate.simulator import Simulator
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import (
CheckpointResource,
obtain_resource,
)
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
requires(isa_required=ISA.ARM)

13
tests/gem5/checkpoint_tests/configs/arm-hello-save-checkpoint.py
View File

@@ -25,17 +25,18 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import argparse
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import obtain_resource
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
PrivateL1PrivateL2CacheHierarchy,
)
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.simulate.simulator import Simulator
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
parser = argparse.ArgumentParser()

16
tests/gem5/checkpoint_tests/configs/power-hello-restore-checkpoint.py
View File

@@ -33,16 +33,18 @@ runs the rest of "power-hello" binary simulation.
This configuration serves as a test of restoring a checkpoint with POWER ISA.
"""
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import obtain_resource, CheckpointResource
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.simulate.simulator import Simulator
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import (
CheckpointResource,
obtain_resource,
)
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
requires(isa_required=ISA.POWER)

13
tests/gem5/checkpoint_tests/configs/power-hello-save-checkpoint.py
View File

@@ -32,15 +32,16 @@ with POWER ISA.
"""
import argparse
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import obtain_resource
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.simulate.simulator import Simulator
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
parser = argparse.ArgumentParser()

16
tests/gem5/checkpoint_tests/configs/sparc-hello-restore-checkpoint.py
View File

@@ -33,16 +33,18 @@ runs the rest of "sparc-hello" binary simulation.
This configuration serves as a test of restoring a checkpoint with SPARC ISA.
"""
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import obtain_resource, CheckpointResource
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.simulate.simulator import Simulator
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import (
CheckpointResource,
obtain_resource,
)
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
requires(isa_required=ISA.SPARC)

13
tests/gem5/checkpoint_tests/configs/sparc-hello-save-checkpoint.py
View File

@@ -32,15 +32,16 @@ with SPARC ISA.
"""
import argparse
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import obtain_resource
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.simulate.simulator import Simulator
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
parser = argparse.ArgumentParser()

11
tests/gem5/checkpoint_tests/configs/x86-fs-restore-checkpoint.py
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@@ -34,16 +34,19 @@ This configuration serves as a test of restoring a checkpoint with X86 ISA in fs
"""
from gem5.components.boards.x86_board import X86Board
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
PrivateL1PrivateL2CacheHierarchy,
)
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import obtain_resource, CheckpointResource
from gem5.resources.resource import (
CheckpointResource,
obtain_resource,
)
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
# Run a check to ensure the right version of gem5 is being used.
requires(isa_required=ISA.X86)

7
tests/gem5/checkpoint_tests/configs/x86-fs-save-checkpoint.py
View File

@@ -32,17 +32,18 @@ with X86 ISA in fs mode.
"""
import argparse
from gem5.components.boards.x86_board import X86Board
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
PrivateL1PrivateL2CacheHierarchy,
)
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
parser = argparse.ArgumentParser()

16
tests/gem5/checkpoint_tests/configs/x86-hello-restore-checkpoint.py
View File

@@ -33,18 +33,20 @@ runs the rest of "x86-hello64-static" binary simulation.
This configuration serves as a test of restoring a checkpoint with X86 ISA.
"""
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import obtain_resource, CheckpointResource
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.private_l1_cache_hierarchy import (
PrivateL1CacheHierarchy,
)
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.simulate.simulator import Simulator
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import (
CheckpointResource,
obtain_resource,
)
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
requires(isa_required=ISA.X86)

13
tests/gem5/checkpoint_tests/configs/x86-hello-save-checkpoint.py
View File

@@ -32,17 +32,18 @@ with X86 ISA.
"""
import argparse
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import obtain_resource
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.private_l1_cache_hierarchy import (
PrivateL1CacheHierarchy,
)
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.simulate.simulator import Simulator
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
parser = argparse.ArgumentParser()

5
tests/gem5/checkpoint_tests/test-checkpoints.py
View File

@@ -28,9 +28,10 @@
This runs simple tests to ensure the examples in `configs/example/gem5_library`
still function. They simply check the simulation completed.
"""
from testlib import *
import re
import os
import re
from testlib import *
if config.bin_path:
resource_path = config.bin_path

2
tests/gem5/cpu_tests/run.py
View File

@@ -24,8 +24,8 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
import argparse
import os
import m5
from m5.objects import *

37
tests/gem5/fixture.py
View File

@@ -36,25 +36,34 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
import tempfile
import shutil
import sys
import socket
import threading
import gzip
import os
import shutil
import socket
import sys
import tempfile
import threading
import urllib.error
import urllib.request
from typing import (
List,
Optional,
)
from testlib.fixture import Fixture
from testlib.configuration import config, constants
from testlib.helper import log_call, cacheresult, joinpath, absdirpath
import testlib.log as log
from testlib.configuration import (
config,
constants,
)
from testlib.fixture import Fixture
from testlib.helper import (
absdirpath,
cacheresult,
joinpath,
log_call,
)
from testlib.state import Result
from typing import Optional, List
class VariableFixture(Fixture):
def __init__(self, value=None, name=None):
@@ -342,7 +351,9 @@ class DownloadedProgram(UniqueFixture):
urllib.request.urlretrieve(self.url, self.filename)
def _getremotetime(self):
import datetime, time
import datetime
import time
import _strptime # Needed for python threading bug
u = urllib.request.urlopen(self.url, timeout=10)

15
tests/gem5/fs/linux/arm/configs/arm_generic.py
View File

@@ -33,19 +33,24 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from abc import ABCMeta, abstractmethod
from abc import (
ABCMeta,
abstractmethod,
)
import m5
from m5.objects import *
from m5.proxy import *
m5.util.addToPath("../configs/")
from common import FSConfig
from base_caches import *
from base_config import *
from common.cores.arm.O3_ARM_v7a import *
from common import (
FSConfig,
SysPaths,
)
from common.Benchmarks import SysConfig
from common import SysPaths
from common.cores.arm.O3_ARM_v7a import *
class ArmSESystemUniprocessor(BaseSESystemUniprocessor):

17
tests/gem5/fs/linux/arm/configs/base_config.py
View File

@@ -33,15 +33,22 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from abc import ABCMeta, abstractmethod
import argparse
from abc import (
ABCMeta,
abstractmethod,
)
from base_caches import *
from common import (
FSConfig,
Options,
)
from ruby import Ruby
import m5
from m5.objects import *
from m5.proxy import *
from common import FSConfig
from common import Options
from base_caches import *
from ruby import Ruby
_have_kvm_support = "BaseKvmCPU" in globals()

4
tests/gem5/fs/linux/arm/configs/checkpoint.py
View File

@@ -33,9 +33,9 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from multiprocessing import Process
import sys
import os
import sys
from multiprocessing import Process
import m5

3
tests/gem5/fs/linux/arm/configs/realview-minor-dual.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSystem(
aarch64_kernel=False,
machine_type="VExpress_GEM5_V1",

3
tests/gem5/fs/linux/arm/configs/realview-minor.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSystemUniprocessor(
aarch64_kernel=False,
machine_type="VExpress_GEM5_V1",

3
tests/gem5/fs/linux/arm/configs/realview-o3-checker.py
View File

@@ -33,10 +33,11 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
from m5.objects import *
root = LinuxArmFSSystemUniprocessor(
aarch64_kernel=False,
machine_type="VExpress_GEM5_V1",

3
tests/gem5/fs/linux/arm/configs/realview-o3-dual.py
View File

@@ -33,10 +33,11 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
from m5.objects import *
root = LinuxArmFSSystem(
aarch64_kernel=False,
machine_type="VExpress_GEM5_V1",

3
tests/gem5/fs/linux/arm/configs/realview-o3.py
View File

@@ -33,10 +33,11 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
from m5.objects import *
root = LinuxArmFSSystemUniprocessor(
aarch64_kernel=False,
machine_type="VExpress_GEM5_V1",

5
tests/gem5/fs/linux/arm/configs/realview-simple-atomic-checkpoint.py
View File

@@ -35,9 +35,10 @@
import functools
from m5.objects import *
from arm_generic import *
import checkpoint
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSystemUniprocessor(
aarch64_kernel=False,

3
tests/gem5/fs/linux/arm/configs/realview-simple-atomic-dual.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSystem(
aarch64_kernel=False,
machine_type="VExpress_GEM5_V1",

3
tests/gem5/fs/linux/arm/configs/realview-simple-atomic.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSystemUniprocessor(
aarch64_kernel=False,
machine_type="VExpress_GEM5_V1",

3
tests/gem5/fs/linux/arm/configs/realview-simple-timing-dual-ruby.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSystem(
aarch64_kernel=False,
machine_type="VExpress_GEM5_V1",

3
tests/gem5/fs/linux/arm/configs/realview-simple-timing-dual.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSystem(
aarch64_kernel=False,
machine_type="VExpress_GEM5_V1",

3
tests/gem5/fs/linux/arm/configs/realview-simple-timing-ruby.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSystemUniprocessor(
aarch64_kernel=False,
machine_type="VExpress_GEM5_V1",

3
tests/gem5/fs/linux/arm/configs/realview-simple-timing.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSystemUniprocessor(
aarch64_kernel=False,
machine_type="VExpress_GEM5_V1",

5
tests/gem5/fs/linux/arm/configs/realview-switcheroo-atomic.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
import switcheroo
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSwitcheroo(
mem_class=SimpleMemory,

5
tests/gem5/fs/linux/arm/configs/realview-switcheroo-full.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
import switcheroo
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSwitcheroo(
machine_type="VExpress_GEM5_V1",

5
tests/gem5/fs/linux/arm/configs/realview-switcheroo-noncaching-timing.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
import switcheroo
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSwitcheroo(
cpu_classes=(ArmNonCachingSimpleCPU, ArmTimingSimpleCPU)

5
tests/gem5/fs/linux/arm/configs/realview-switcheroo-o3.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
import switcheroo
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSwitcheroo(
aarch64_kernel=False,

5
tests/gem5/fs/linux/arm/configs/realview-switcheroo-timing.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
import switcheroo
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSwitcheroo(
mem_class=DDR3_1600_8x8,

8
tests/gem5/fs/linux/arm/configs/realview64-kvm-dual.py
View File

@@ -33,9 +33,13 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from m5.ticks import fixGlobalFrequency, fromSeconds
from m5.objects import *
from m5.ticks import (
fixGlobalFrequency,
fromSeconds,
)
root = LinuxArmFSSystem(
mem_mode="atomic_noncaching",

3
tests/gem5/fs/linux/arm/configs/realview64-kvm.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSystemUniprocessor(
mem_mode="atomic_noncaching",
machine_type="VExpress_GEM5_V1",

3
tests/gem5/fs/linux/arm/configs/realview64-minor-dual.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSystem(
mem_mode="timing",
mem_class=DDR3_1600_8x8,

3
tests/gem5/fs/linux/arm/configs/realview64-minor.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSystemUniprocessor(
mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=ArmMinorCPU
).create_root()

3
tests/gem5/fs/linux/arm/configs/realview64-o3-checker.py
View File

@@ -33,10 +33,11 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
from m5.objects import *
root = LinuxArmFSSystemUniprocessor(
mem_mode="timing",
machine_type="VExpress_GEM5_V1",

3
tests/gem5/fs/linux/arm/configs/realview64-o3-dual-ruby.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSystem(
mem_mode="timing",
mem_class=DDR3_1600_8x8,

3
tests/gem5/fs/linux/arm/configs/realview64-o3-dual.py
View File

@@ -33,10 +33,11 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
from m5.objects import *
root = LinuxArmFSSystem(
mem_mode="timing",
mem_class=DDR3_1600_8x8,

3
tests/gem5/fs/linux/arm/configs/realview64-o3.py
View File

@@ -33,10 +33,11 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
from m5.objects import *
root = LinuxArmFSSystemUniprocessor(
mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=O3_ARM_v7a_3
).create_root()

5
tests/gem5/fs/linux/arm/configs/realview64-simple-atomic-checkpoint.py
View File

@@ -35,9 +35,10 @@
import functools
from m5.objects import *
from arm_generic import *
import checkpoint
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSystemUniprocessor(
mem_mode="atomic", mem_class=SimpleMemory, cpu_class=ArmAtomicSimpleCPU

3
tests/gem5/fs/linux/arm/configs/realview64-simple-atomic-dual.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSystem(
mem_mode="atomic",
mem_class=SimpleMemory,

3
tests/gem5/fs/linux/arm/configs/realview64-simple-atomic.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSystemUniprocessor(
mem_mode="atomic", mem_class=SimpleMemory, cpu_class=ArmAtomicSimpleCPU
).create_root()

3
tests/gem5/fs/linux/arm/configs/realview64-simple-timing-dual-ruby.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSystem(
mem_mode="timing",
mem_class=DDR3_1600_8x8,

3
tests/gem5/fs/linux/arm/configs/realview64-simple-timing-dual.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSystem(
mem_mode="timing",
mem_class=DDR3_1600_8x8,

3
tests/gem5/fs/linux/arm/configs/realview64-simple-timing-ruby.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSystemUniprocessor(
mem_mode="timing",
mem_class=DDR3_1600_8x8,

3
tests/gem5/fs/linux/arm/configs/realview64-simple-timing.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSystemUniprocessor(
mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=ArmTimingSimpleCPU
).create_root()

5
tests/gem5/fs/linux/arm/configs/realview64-switcheroo-atomic.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
import switcheroo
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSwitcheroo(
mem_class=SimpleMemory,

5
tests/gem5/fs/linux/arm/configs/realview64-switcheroo-full.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
import switcheroo
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSwitcheroo(
mem_class=DDR3_1600_8x8,

5
tests/gem5/fs/linux/arm/configs/realview64-switcheroo-o3.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
import switcheroo
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSwitcheroo(
mem_class=DDR3_1600_8x8, cpu_classes=(ArmO3CPU, ArmO3CPU)

5
tests/gem5/fs/linux/arm/configs/realview64-switcheroo-timing.py
View File

@@ -33,9 +33,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import *
from arm_generic import *
import switcheroo
from arm_generic import *
from m5.objects import *
root = LinuxArmFSSwitcheroo(
mem_class=DDR3_1600_8x8,

3
tests/gem5/fs/linux/arm/configs/switcheroo.py
View File

@@ -34,9 +34,10 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import m5
import _m5
from m5.objects import *
import _m5
m5.util.addToPath("../configs/")
from base_caches import *

2
tests/gem5/fs/linux/arm/run.py
View File

@@ -36,9 +36,9 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import sys
import os
import os.path
import sys
from os.path import join as joinpath
import m5

3
tests/gem5/fs/linux/arm/test.py
View File

@@ -37,12 +37,11 @@
Arm FS simulation tests
"""
import re
from os.path import join as joinpath
from testlib import *
import re
arm_fs_kvm_tests = ["realview64-kvm", "realview64-kvm-dual"]
arm_fs_quick_tests = [

5
tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
View File

@@ -28,10 +28,11 @@
This runs simple tests to ensure the examples in `configs/example/gem5_library`
still function. They simply check the simulation completed.
"""
import os
import re
from testlib import *
from testlib.log import *
import re
import os
if config.bin_path:
resource_path = config.bin_path

18
tests/gem5/gem5_resources/configs/download_check.py
View File

@@ -24,20 +24,18 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from gem5.resources.downloader import (
list_resources,
get_resource,
)
from gem5.resources.client import get_resource_json_obj
from gem5.resources.md5_utils import md5
import argparse
import os
import shutil
import argparse
from pathlib import Path
from gem5.resources.client import get_resource_json_obj
from gem5.resources.downloader import (
get_resource,
list_resources,
)
from gem5.resources.md5_utils import md5
parser = argparse.ArgumentParser(
description="A script that will checks that input resource IDs will "
"download a resource and that resources md5 value is correct. "

40
tests/gem5/insttest_se/configs/simple_binary_run.py
View File

@@ -31,27 +31,31 @@ The system has no cache heirarchy and is as "bare-bones" as you can get in
gem5 while still being functinal.
"""
from gem5.resources.resource import Resource
from gem5.components.processors.cpu_types import (
get_cpu_types_str_set,
get_cpu_type_from_str,
)
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.base_cpu_core import BaseCPUCore
from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
from gem5.components.processors.simple_core import SimpleCore
from gem5.components.boards.mem_mode import MemMode
from gem5.components.processors.cpu_types import CPUTypes
from gem5.simulate.simulator import Simulator
from gem5.isas import get_isa_from_str, get_isas_str_set, ISA
import argparse
import importlib
from m5.util import fatal
import argparse
import importlib
from gem5.components.boards.mem_mode import MemMode
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.base_cpu_core import BaseCPUCore
from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
from gem5.components.processors.cpu_types import (
CPUTypes,
get_cpu_type_from_str,
get_cpu_types_str_set,
)
from gem5.components.processors.simple_core import SimpleCore
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import (
ISA,
get_isa_from_str,
get_isas_str_set,
)
from gem5.resources.resource import Resource
from gem5.simulate.simulator import Simulator
cpu_types_string_map = {
CPUTypes.ATOMIC: "AtomicSimpleCPU",

6
tests/gem5/kvm_fork_tests/configs/boot_kvm_fork_run.py
View File

@@ -43,18 +43,18 @@ from textwrap import dedent
import m5
from m5.objects import Root
from gem5.components.boards.x86_board import X86Board
from gem5.coherence_protocol import CoherenceProtocol
from gem5.isas import ISA
from gem5.components.boards.x86_board import X86Board
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import (
CPUTypes,
get_cpu_types_str_set,
get_cpu_type_from_str,
get_cpu_types_str_set,
)
from gem5.components.processors.simple_switchable_processor import (
SimpleSwitchableProcessor,
)
from gem5.isas import ISA
from gem5.resources.resource import obtain_resource
from gem5.runtime import get_runtime_coherence_protocol
from gem5.utils.requires import requires

8
tests/gem5/kvm_switch_tests/configs/boot_kvm_switch_exit.py
View File

@@ -33,22 +33,22 @@ import argparse
import m5
from m5.objects import Root
from gem5.isas import ISA
from gem5.components.boards.x86_board import X86Board
from gem5.coherence_protocol import CoherenceProtocol
from gem5.components.boards.x86_board import X86Board
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import (
CPUTypes,
get_cpu_types_str_set,
get_cpu_type_from_str,
get_cpu_types_str_set,
)
from gem5.components.processors.simple_switchable_processor import (
SimpleSwitchableProcessor,
)
from gem5.isas import ISA
from gem5.resources.resource import obtain_resource
from gem5.runtime import get_runtime_coherence_protocol
from gem5.simulate.simulator import Simulator
from gem5.simulate.exit_event import ExitEvent
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
parser = argparse.ArgumentParser(

41
tests/gem5/m5_util/configs/simple_binary_run.py
View File

@@ -31,28 +31,31 @@ The system has no cache heirarchy and is as "bare-bones" as you can get in
gem5 while still being functinal.
"""
from gem5.resources.resource import Resource
from gem5.components.processors.cpu_types import (
get_cpu_types_str_set,
get_cpu_type_from_str,
)
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.base_cpu_core import BaseCPUCore
from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
from gem5.components.processors.simple_core import SimpleCore
from gem5.components.boards.mem_mode import MemMode
from gem5.components.processors.cpu_types import CPUTypes
from gem5.simulate.simulator import Simulator
from gem5.isas import get_isa_from_str, get_isas_str_set, ISA
from m5.util import fatal
import argparse
import importlib
from m5.util import fatal
from gem5.components.boards.mem_mode import MemMode
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.base_cpu_core import BaseCPUCore
from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
from gem5.components.processors.cpu_types import (
CPUTypes,
get_cpu_type_from_str,
get_cpu_types_str_set,
)
from gem5.components.processors.simple_core import SimpleCore
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import (
ISA,
get_isa_from_str,
get_isas_str_set,
)
from gem5.resources.resource import Resource
from gem5.simulate.simulator import Simulator
parser = argparse.ArgumentParser(
description="A gem5 script for running simple binaries in SE mode."

1
tests/gem5/m5_util/test_exit.py
View File

@@ -40,6 +40,7 @@
Test file for the util m5 exit assembly instruction.
"""
import re
from testlib import *
m5_exit_regex = re.compile(

8
tests/gem5/m5threads_test_atomic/atomic_system.py
View File

@@ -24,11 +24,13 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import argparse
import sys
from caches import *
import m5
from m5.objects import *
from caches import *
import sys
import argparse
parser = argparse.ArgumentParser(description="m5threads atomic tester")
parser.add_argument("--cpu-type", default="DerivO3CPU")

13
tests/gem5/m5threads_test_atomic/caches.py
View File

@@ -31,8 +31,17 @@ gem5 configuration script.
"""
import m5
from m5.objects import Cache, L2XBar, StridePrefetcher, SubSystem
from m5.params import AddrRange, AllMemory, MemorySize
from m5.objects import (
Cache,
L2XBar,
StridePrefetcher,
SubSystem,
)
from m5.params import (
AddrRange,
AllMemory,
MemorySize,
)
from m5.util.convert import toMemorySize
# Some specific options for caches

4
tests/gem5/memory/simple-run.py
View File

@@ -33,11 +33,11 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import argparse
import m5
from m5.objects import *
import argparse
parser = argparse.ArgumentParser(description="Simple memory tester")
parser.add_argument("--bandwidth", default=None)
parser.add_argument("--latency", default=None)

10
tests/gem5/multi_isa/configs/runtime_isa_check.py
View File

@@ -29,11 +29,15 @@ This is a very simple script to test the output given by
`gem5.runtime.get_runtime_isa`
"""
from gem5.runtime import get_runtime_isa
from gem5.isas import ISA, get_isas_str_set, get_isa_from_str
import argparse
from gem5.isas import (
ISA,
get_isa_from_str,
get_isas_str_set,
)
from gem5.runtime import get_runtime_isa
parser = argparse.ArgumentParser(
description="A simple script used to check the output of "
"`gem5.runtime.get_runtime_isa`"

11
tests/gem5/multi_isa/configs/supported_isa_check.py
View File

@@ -29,11 +29,14 @@ This is a very simple script to test the output given by
`gem5.runtime.get_supported_isas`
"""
from gem5.runtime import get_supported_isas
from gem5.isas import get_isas_str_set, get_isa_from_str
import os
import argparse
import os
from gem5.isas import (
get_isa_from_str,
get_isas_str_set,
)
from gem5.runtime import get_supported_isas
parser = argparse.ArgumentParser(
description="A simple script used to check the output of "

23
tests/gem5/parsec_benchmarks/configs/parsec_disk_run.py
View File

@@ -35,27 +35,30 @@ Notes
* This will only function for the X86 ISA.
"""
import argparse
import time
import m5.stats
from gem5.resources.resource import obtain_resource
from gem5.components.boards.x86_board import X86Board
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import (
get_cpu_type_from_str,
get_cpu_types_str_set,
)
from gem5.components.processors.simple_switchable_processor import (
SimpleSwitchableProcessor,
)
from gem5.components.processors.cpu_types import (
get_cpu_types_str_set,
get_cpu_type_from_str,
)
from gem5.isas import ISA
from gem5.runtime import get_runtime_isa, get_runtime_coherence_protocol
from gem5.simulate.simulator import Simulator
from gem5.resources.resource import obtain_resource
from gem5.runtime import (
get_runtime_coherence_protocol,
get_runtime_isa,
)
from gem5.simulate.exit_event import ExitEvent
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
import time
import argparse
requires(isa_required=ISA.X86)

7
tests/gem5/replacement_policies/configs/cache_hierarchies.py
View File

@@ -27,12 +27,13 @@
from typing import Type
from gem5.utils.override import overrides
from m5.objects.ReplacementPolicies import BaseReplacementPolicy
from gem5.components.boards.abstract_board import AbstractBoard
from gem5.components.cachehierarchies.ruby.mi_example_cache_hierarchy import (
MIExampleCacheHierarchy,
)
from gem5.components.boards.abstract_board import AbstractBoard
from m5.objects.ReplacementPolicies import BaseReplacementPolicy
from gem5.utils.override import overrides
class ModMIExampleCacheHierarchy(MIExampleCacheHierarchy):

2
tests/gem5/replacement_policies/configs/run_replacement_policy.py
View File

@@ -30,9 +30,9 @@ from importlib.machinery import SourceFileLoader
from cache_hierarchies import ModMIExampleCacheHierarchy
import m5
from m5.debug import flags
from m5.objects import Root
from gem5.components.boards.test_board import TestBoard
from gem5.components.memory.simple import SingleChannelSimpleMemory
from gem5.components.processors.complex_generator import ComplexGenerator

2
tests/gem5/replacement_policies/run_replacement_policy.py
View File

@@ -30,9 +30,9 @@ from importlib.machinery import SourceFileLoader
from cache_hierarchies import ModMIExampleCacheHierarchy
import m5
from m5.debug import flags
from m5.objects import Root
from gem5.components.boards.test_board import TestBoard
from gem5.components.memory.simple import SingleChannelSimpleMemory
from gem5.components.processors.complex_generator import ComplexGenerator

20
tests/gem5/riscv_boot_tests/configs/riscv_boot_exit_run.py
View File

@@ -33,18 +33,20 @@ Characteristics
* Runs exclusively on the RISC-V ISA with the classic caches
"""
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import Resource
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.boards.riscv_board import RiscvBoard
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.simulate.simulator import Simulator
from gem5.resources.resource import obtain_resource
import argparse
import importlib
from gem5.components.boards.riscv_board import RiscvBoard
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import (
Resource,
obtain_resource,
)
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
parser = argparse.ArgumentParser(
description="A script to run the RISCV boot exit tests."
)

1
tests/gem5/riscv_boot_tests/test_linux_boot.py
View File

@@ -25,7 +25,6 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import re
from typing import Optional
from testlib import *

40
tests/gem5/se_mode/hello_se/configs/simple_binary_run.py
View File

@@ -31,27 +31,31 @@ The system has no cache heirarchy and is as "bare-bones" as you can get in
gem5 while still being functinal.
"""
from gem5.resources.resource import obtain_resource
from gem5.components.processors.cpu_types import (
get_cpu_types_str_set,
get_cpu_type_from_str,
)
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.base_cpu_core import BaseCPUCore
from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
from gem5.components.processors.simple_core import SimpleCore
from gem5.components.boards.mem_mode import MemMode
from gem5.components.processors.cpu_types import CPUTypes
from gem5.simulate.simulator import Simulator
from gem5.isas import get_isa_from_str, get_isas_str_set, ISA
import argparse
import importlib
from m5.util import fatal
import argparse
import importlib
from gem5.components.boards.mem_mode import MemMode
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.base_cpu_core import BaseCPUCore
from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
from gem5.components.processors.cpu_types import (
CPUTypes,
get_cpu_type_from_str,
get_cpu_types_str_set,
)
from gem5.components.processors.simple_core import SimpleCore
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import (
ISA,
get_isa_from_str,
get_isas_str_set,
)
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
cpu_types_string_map = {
CPUTypes.ATOMIC: "AtomicSimpleCPU",

4
tests/gem5/se_mode/hello_se/test_hello_se.py
View File

@@ -43,10 +43,10 @@
Tests which run simple binaries in gem5's SE mode. The stdlib's SimpleBoard
is used to run these tests.
"""
from testlib import *
import re
from testlib import *
isa_str_map = {
constants.gcn3_x86_tag: "x86",
constants.arm_tag: "arm",

40
tests/gem5/stats/configs/simple_binary_run.py
View File

@@ -31,27 +31,31 @@ The system has no cache heirarchy and is as "bare-bones" as you can get in
gem5 while still being functinal.
"""
from gem5.resources.resource import Resource
from gem5.components.processors.cpu_types import (
get_cpu_types_str_set,
get_cpu_type_from_str,
)
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.base_cpu_core import BaseCPUCore
from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
from gem5.components.processors.simple_core import SimpleCore
from gem5.components.boards.mem_mode import MemMode
from gem5.components.processors.cpu_types import CPUTypes
from gem5.simulate.simulator import Simulator
from gem5.isas import get_isa_from_str, get_isas_str_set, ISA
import argparse
import importlib
from m5.util import fatal
import argparse
import importlib
from gem5.components.boards.mem_mode import MemMode
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.base_cpu_core import BaseCPUCore
from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
from gem5.components.processors.cpu_types import (
CPUTypes,
get_cpu_type_from_str,
get_cpu_types_str_set,
)
from gem5.components.processors.simple_core import SimpleCore
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import (
ISA,
get_isa_from_str,
get_isas_str_set,
)
from gem5.resources.resource import Resource
from gem5.simulate.simulator import Simulator
parser = argparse.ArgumentParser(
description="A gem5 script for running simple binaries in SE mode."

3
tests/gem5/stats/test_hdf5.py
View File

@@ -46,8 +46,9 @@ It will not run if the build/ARM/gem5.opt has not been built. As this is not
built prior to this test being processed during the Weekly run, this test is
not run.
"""
import re
import os
import re
from testlib import *
if config.bin_path:

11
tests/gem5/stdlib/configs/requires_check.py
View File

@@ -28,12 +28,15 @@
This is a very simple script to test the behavior of 'gem5.utils.requires'`
"""
from gem5.utils.requires import requires
from gem5.isas import ISA, get_isas_str_set, get_isa_from_str
import argparse
from gem5.isas import (
ISA,
get_isa_from_str,
get_isas_str_set,
)
from gem5.utils.requires import requires
parser = argparse.ArgumentParser(
description="A simple script used to check the behavior of "
"`gem5.utils.requires`."

40
tests/gem5/stdlib/configs/simple_binary_run.py
View File

@@ -31,27 +31,31 @@ The system has no cache heirarchy and is as "bare-bones" as you can get in
gem5 while still being functinal.
"""
from gem5.resources.resource import Resource
from gem5.components.processors.cpu_types import (
get_cpu_types_str_set,
get_cpu_type_from_str,
)
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.base_cpu_core import BaseCPUCore
from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
from gem5.components.processors.simple_core import SimpleCore
from gem5.components.boards.mem_mode import MemMode
from gem5.components.processors.cpu_types import CPUTypes
from gem5.simulate.simulator import Simulator
from gem5.isas import get_isa_from_str, get_isas_str_set, ISA
import argparse
import importlib
from m5.util import fatal
import argparse
import importlib
from gem5.components.boards.mem_mode import MemMode
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.base_cpu_core import BaseCPUCore
from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
from gem5.components.processors.cpu_types import (
CPUTypes,
get_cpu_type_from_str,
get_cpu_types_str_set,
)
from gem5.components.processors.simple_core import SimpleCore
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import (
ISA,
get_isa_from_str,
get_isas_str_set,
)
from gem5.resources.resource import Resource
from gem5.simulate.simulator import Simulator
cpu_types_string_map = {
CPUTypes.ATOMIC: "AtomicSimpleCPU",

13
tests/gem5/stdlib/configs/simulator_exit_event_run.py
View File

@@ -46,18 +46,17 @@ functions or a lone function can also be passed. This can be specified by the
`--exit-event-type` parameter.
"""
from gem5.resources.resource import obtain_resource
from gem5.components.memory import SingleChannelDDR3_1600
import argparse
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.boards.simple_board import SimpleBoard
from gem5.simulate.simulator import Simulator
from gem5.simulate.exit_event import ExitEvent
from gem5.isas import ISA
import argparse
from gem5.resources.resource import obtain_resource
from gem5.simulate.exit_event import ExitEvent
from gem5.simulate.simulator import Simulator
parser = argparse.ArgumentParser(
description="A gem5 script for running simple binaries in SE mode."

17
tests/gem5/suite.py
View File

@@ -36,18 +36,25 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
import copy
import os
import subprocess
import sys
from testlib.test_util import TestFunction
from testlib.suite import TestSuite
from testlib.configuration import (
config,
constants,
)
from testlib.helper import log_call
from testlib.configuration import constants, config
from .fixture import TempdirFixture, Gem5Fixture, VariableFixture
from testlib.suite import TestSuite
from testlib.test_util import TestFunction
from . import verifier
from .fixture import (
Gem5Fixture,
TempdirFixture,
VariableFixture,
)
def gem5_verify_config(

20
tests/gem5/to_tick/configs/tick-exit.py
View File

@@ -28,19 +28,19 @@
"""
from gem5.resources.resource import obtain_resource
from gem5.isas import ISA
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.cpu_types import CPUTypes
from gem5.simulate.simulator import Simulator
from gem5.simulate.exit_event import ExitEvent
import argparse
import m5
import argparse
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import obtain_resource
from gem5.simulate.exit_event import ExitEvent
from gem5.simulate.simulator import Simulator
parser = argparse.ArgumentParser()

18
tests/gem5/to_tick/configs/tick-to-max.py
View File

@@ -33,18 +33,18 @@ run before, at, or after the running of `simulator.run`.
time.
"""
from gem5.resources.resource import obtain_resource
from gem5.isas import ISA
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.cpu_types import CPUTypes
from gem5.simulate.simulator import Simulator
import argparse
import m5
import argparse
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
parser = argparse.ArgumentParser()

9
tests/gem5/traffic_gen/configs/simple_traffic_run.py
View File

@@ -31,14 +31,17 @@ subsystem. The reported values could be used to compare against a validated
set of statistics.
"""
import m5
import argparse
import importlib
from pathlib import Path
from m5.objects import Root, MemorySize
import m5
from m5.objects import (
MemorySize,
Root,
)
from m5.stats.gem5stats import get_simstat
from gem5.components.boards.test_board import TestBoard

9
tests/gem5/verifier.py
View File

@@ -40,13 +40,16 @@
"""
Built in test cases that verify particular details about a gem5 run.
"""
import re
import os
import json
import os
import re
from testlib import test_util
from testlib.configuration import constants
from testlib.helper import joinpath, diff_out_file
from testlib.helper import (
diff_out_file,
joinpath,
)
class Verifier:

29
tests/gem5/x86_boot_tests/configs/x86_boot_exit_run.py
View File

@@ -28,24 +28,23 @@
This script will run a simple boot exit test.
"""
import m5
from gem5.runtime import get_runtime_coherence_protocol
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.coherence_protocol import CoherenceProtocol
from gem5.components.boards.x86_board import X86Board
from gem5.components.processors.cpu_types import (
get_cpu_types_str_set,
get_cpu_type_from_str,
)
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.simulate.simulator import Simulator
from gem5.resources.resource import obtain_resource
import argparse
import importlib
import m5
from gem5.coherence_protocol import CoherenceProtocol
from gem5.components.boards.x86_board import X86Board
from gem5.components.processors.cpu_types import (
get_cpu_type_from_str,
get_cpu_types_str_set,
)
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import obtain_resource
from gem5.runtime import get_runtime_coherence_protocol
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
parser = argparse.ArgumentParser(
description="A script to run the gem5 boot test. This test boots the "

2
tests/gem5/x86_boot_tests/test_linux_boot.py
View File

@@ -24,8 +24,8 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from typing import Optional
import re
from typing import Optional
from testlib import *

4
tests/main.py
View File

@@ -6,8 +6,8 @@ loaders.
Discovers and runs all tests from a given root directory.
"""
import sys
import os
import sys
os.environ["PYTHONUNBUFFERED"] = "1"
@@ -17,9 +17,9 @@ ext_path = os.path.join(base_dir, os.pardir, "ext")
sys.path.insert(0, base_dir)
sys.path.insert(0, ext_path)
import testlib.main as testlib
import testlib.configuration as config
import testlib.helper as helper
import testlib.main as testlib
config.basedir = helper.absdirpath(__file__)
sys.exit(testlib())

1
tests/pyunit/pyunit_jsonserializable_check.py
View File

@@ -25,6 +25,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import unittest
from m5.ext.pystats.serializable_stat import SerializableStat

9
tests/pyunit/stdlib/pyunit_looppoint.py
View File

@@ -24,22 +24,21 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
import unittest
from m5.params import PcCountPair
from gem5.resources.looppoint import (
Looppoint,
LooppointCsvLoader,
LooppointJsonLoader,
LooppointRegion,
LooppointRegionPC,
LooppointRegionWarmup,
LooppointSimulation,
LooppointRegion,
LooppointCsvLoader,
LooppointJsonLoader,
)
import os
class LooppointRegionPCTestSuite(unittest.TestCase):
"""Tests the resources.looppoint.LooppointRegionPC class."""

14
tests/pyunit/stdlib/resources/pyunit_client_wrapper_checks.py
View File

@@ -24,19 +24,19 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import unittest
from gem5.resources.client import get_resource_json_obj
from gem5.resources.client_api.client_wrapper import ClientWrapper
from unittest.mock import patch
import json
from urllib.error import HTTPError
import io
import contextlib
import io
import json
import unittest
from pathlib import Path
from unittest.mock import patch
from urllib.error import HTTPError
from gem5.resources.client import get_resource_json_obj
from gem5.resources.client_api.atlasclient import (
AtlasClientHttpJsonRequestError,
)
from gem5.resources.client_api.client_wrapper import ClientWrapper
mock_json_path = Path(__file__).parent / "refs/resources.json"
mock_config_json = {

8
tests/pyunit/stdlib/resources/pyunit_json_client_checks.py
View File

@@ -24,11 +24,11 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import unittest
import tempfile
import os
from typing import Dict
import json
import os
import tempfile
import unittest
from typing import Dict
from gem5.resources.client_api.jsonclient import JSONClient

5
tests/pyunit/stdlib/resources/pyunit_local_file_path_check.py
View File

@@ -24,9 +24,10 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from gem5.resources.downloader import _file_uri_to_path
from pathlib import Path
import unittest
from pathlib import Path
from gem5.resources.downloader import _file_uri_to_path
class LocalPathTestSuite(unittest.TestCase):

9
tests/pyunit/stdlib/resources/pyunit_md5_utils_check.py
View File

@@ -24,13 +24,16 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import unittest
import tempfile
import os
import shutil
import tempfile
import unittest
from pathlib import Path
from gem5.resources.md5_utils import md5_file, md5_dir
from gem5.resources.md5_utils import (
md5_dir,
md5_file,
)
class MD5FileTestSuite(unittest.TestCase):

17
tests/pyunit/stdlib/resources/pyunit_obtain_resources_check.py
View File

@@ -24,20 +24,21 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import unittest
import os
import io
import contextlib
import io
import os
import unittest
from pathlib import Path
from gem5.resources.resource import obtain_resource, BinaryResource
from gem5.isas import ISA
from unittest.mock import patch
from _m5 import core
from gem5.isas import ISA
from gem5.resources.client_api.client_wrapper import ClientWrapper
from unittest.mock import patch
from gem5.resources.resource import (
BinaryResource,
obtain_resource,
)
mock_json_path = Path(__file__).parent / "refs/obtain-resource.json"

11
tests/pyunit/stdlib/resources/pyunit_resource_specialization.py
View File

@@ -27,18 +27,15 @@
import os
import unittest
from pathlib import Path
from unittest.mock import patch
from gem5.resources.resource import *
from gem5.isas import ISA
from gem5.resources.client_api.client_wrapper import ClientWrapper
from gem5.resources.looppoint import (
LooppointCsvLoader,
LooppointJsonLoader,
)
from gem5.isas import ISA
from gem5.resources.client_api.client_wrapper import ClientWrapper
from unittest.mock import patch
from gem5.resources.resource import *
mock_json_path = Path(__file__).parent / "refs/resource-specialization.json"

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