derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-arm, cpu, configs: Add new Op Classes for Matrix Multiply insts

Browse Source 
Add SimdMatMultAcc and SimdFloatMatMultAcc Op Classes for the SVE
Matrix Multiply Accumulate instructions in the SVE F32MM, F64MM and
I8MM extensions.

Initial latencies have been set to be the same as SimdMultAcc and
SimdFloatMultAcc respectively.

Change-Id: Ifab63a0efbb0ccfbd272245e0b0b055279f66e3a
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70734
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Richard Cooper
2020-10-28 22:10:01 +00:00
committed by Bobby Bruce
parent 560df49c28
commit d02ea0dfbb
9 changed files with 23 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/cpu/FuncUnit.py
View File

@@ -1,4 +1,4 @@
# Copyright (c) 2010, 2017-2018, 2022 ARM Limited
# Copyright (c) 2010, 2017-2018, 2020, 2022 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -62,6 +62,7 @@ class OpClass(Enum):
"SimdMisc",
"SimdMult",
"SimdMultAcc",
"SimdMatMultAcc",
"SimdShift",
"SimdShiftAcc",
"SimdDiv",
@@ -74,6 +75,7 @@ class OpClass(Enum):
"SimdFloatMisc",
"SimdFloatMult",
"SimdFloatMultAcc",
"SimdFloatMatMultAcc",
"SimdFloatSqrt",
"SimdReduceAdd",
"SimdReduceAlu",