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arch-arm, cpu, configs: Add new Op Classes for Matrix Multiply insts

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Add SimdMatMultAcc and SimdFloatMatMultAcc Op Classes for the SVE
Matrix Multiply Accumulate instructions in the SVE F32MM, F64MM and
I8MM extensions.

Initial latencies have been set to be the same as SimdMultAcc and
SimdFloatMultAcc respectively.

Change-Id: Ifab63a0efbb0ccfbd272245e0b0b055279f66e3a
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70734
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Richard Cooper
2020-10-28 22:10:01 +00:00
committed by Bobby Bruce
parent 560df49c28
commit d02ea0dfbb
9 changed files with 23 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/arch/arm/isa/insts/sve.isa
View File

@@ -3971,7 +3971,7 @@ let {{
fplibMul<DestElement>(srcElemA, srcElemB, fpscr), fpscr);
'''
# FMMLA (vectors)
sveMatMulInst('fmmla', 'Fmmla', 'SimdFloatMultAccOp', floatTypes,
sveMatMulInst('fmmla', 'Fmmla', 'SimdFloatMatMultAccOp', floatTypes,
numDestRows=2, numDestCols=2, K=2,
elt_mul_op=fmmlaCode)
@@ -4265,17 +4265,17 @@ let {{
sbclbCode, isTop=False, isAdd=False)
mmlaCode = ('destElem += srcElemA * srcElemB')
# SMMLA (vectors)
sveMatMulInst('smmla', 'Smmla', 'SimdMultAccOp',
sveMatMulInst('smmla', 'Smmla', 'SimdMatMultAccOp',
(('int32_t', 'int8_t', 'int8_t'),),
numDestRows=2, numDestCols=2, K=8,
elt_mul_op=mmlaCode)
# USMMLA (vectors)
sveMatMulInst('usmmla', 'Usmmla', 'SimdMultAccOp',
sveMatMulInst('usmmla', 'Usmmla', 'SimdMatMultAccOp',
(('int32_t', 'uint8_t', 'int8_t'),),
numDestRows=2, numDestCols=2, K=8,
elt_mul_op=mmlaCode)
# UMMLA (vectors)
sveMatMulInst('ummla', 'Ummla', 'SimdMultAccOp',
sveMatMulInst('ummla', 'Ummla', 'SimdMatMultAccOp',
(('uint32_t', 'uint8_t', 'uint8_t'),),
numDestRows=2, numDestCols=2, K=8,
elt_mul_op=mmlaCode)

4
src/cpu/FuncUnit.py
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@@ -1,4 +1,4 @@
# Copyright (c) 2010, 2017-2018, 2022 ARM Limited
# Copyright (c) 2010, 2017-2018, 2020, 2022 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -62,6 +62,7 @@ class OpClass(Enum):
"SimdMisc",
"SimdMult",
"SimdMultAcc",
"SimdMatMultAcc",
"SimdShift",
"SimdShiftAcc",
"SimdDiv",
@@ -74,6 +75,7 @@ class OpClass(Enum):
"SimdFloatMisc",
"SimdFloatMult",
"SimdFloatMultAcc",
"SimdFloatMatMultAcc",
"SimdFloatSqrt",
"SimdReduceAdd",
"SimdReduceAlu",

2
src/cpu/minor/BaseMinorCPU.py
View File

@@ -189,6 +189,7 @@ class MinorDefaultFloatSimdFU(MinorFU):
"SimdMisc",
"SimdMult",
"SimdMultAcc",
"SimdMatMultAcc",
"SimdShift",
"SimdShiftAcc",
"SimdDiv",
@@ -201,6 +202,7 @@ class MinorDefaultFloatSimdFU(MinorFU):
"SimdFloatMisc",
"SimdFloatMult",
"SimdFloatMultAcc",
"SimdFloatMatMultAcc",
"SimdFloatSqrt",
"SimdReduceAdd",
"SimdReduceAlu",

4
src/cpu/o3/FuncUnitConfig.py
View File

@@ -1,4 +1,4 @@
# Copyright (c) 2010, 2017 ARM Limited
# Copyright (c) 2010, 2017, 2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -87,6 +87,7 @@ class SIMD_Unit(FUDesc):
OpDesc(opClass="SimdMisc"),
OpDesc(opClass="SimdMult"),
OpDesc(opClass="SimdMultAcc"),
OpDesc(opClass="SimdMatMultAcc"),
OpDesc(opClass="SimdShift"),
OpDesc(opClass="SimdShiftAcc"),
OpDesc(opClass="SimdDiv"),
@@ -99,6 +100,7 @@ class SIMD_Unit(FUDesc):
OpDesc(opClass="SimdFloatMisc"),
OpDesc(opClass="SimdFloatMult"),
OpDesc(opClass="SimdFloatMultAcc"),
OpDesc(opClass="SimdFloatMatMultAcc"),
OpDesc(opClass="SimdFloatSqrt"),
OpDesc(opClass="SimdReduceAdd"),
OpDesc(opClass="SimdReduceAlu"),

4
src/cpu/op_class.hh
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010, 2017-2018, 2022 ARM Limited
* Copyright (c) 2010, 2017-2018, 2020, 2022 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -72,6 +72,7 @@ static const OpClass SimdCvtOp = enums::SimdCvt;
static const OpClass SimdMiscOp = enums::SimdMisc;
static const OpClass SimdMultOp = enums::SimdMult;
static const OpClass SimdMultAccOp = enums::SimdMultAcc;
static const OpClass SimdMatMultAccOp = enums::SimdMatMultAcc;
static const OpClass SimdShiftOp = enums::SimdShift;
static const OpClass SimdShiftAccOp = enums::SimdShiftAcc;
static const OpClass SimdDivOp = enums::SimdDiv;
@@ -87,6 +88,7 @@ static const OpClass SimdFloatDivOp = enums::SimdFloatDiv;
static const OpClass SimdFloatMiscOp = enums::SimdFloatMisc;
static const OpClass SimdFloatMultOp = enums::SimdFloatMult;
static const OpClass SimdFloatMultAccOp = enums::SimdFloatMultAcc;
static const OpClass SimdFloatMatMultAccOp = enums::SimdFloatMatMultAcc;
static const OpClass SimdFloatSqrtOp = enums::SimdFloatSqrt;
static const OpClass SimdFloatReduceCmpOp = enums::SimdFloatReduceCmp;
static const OpClass SimdFloatReduceAddOp = enums::SimdFloatReduceAdd;