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arch-arm, cpu, configs: Add new Op Classes for Matrix Multiply insts

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Add SimdMatMultAcc and SimdFloatMatMultAcc Op Classes for the SVE
Matrix Multiply Accumulate instructions in the SVE F32MM, F64MM and
I8MM extensions.

Initial latencies have been set to be the same as SimdMultAcc and
SimdFloatMultAcc respectively.

Change-Id: Ifab63a0efbb0ccfbd272245e0b0b055279f66e3a
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70734
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Richard Cooper
2020-10-28 22:10:01 +00:00
committed by Bobby Bruce
parent 560df49c28
commit d02ea0dfbb
9 changed files with 23 additions and 7 deletions
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2
configs/common/cores/arm/HPI.py
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@@ -1420,6 +1420,7 @@ class HPI_FloatSimdFU(MinorFU):
"SimdMisc",
"SimdMult",
"SimdMultAcc",
"SimdMatMultAcc",
"SimdShift",
"SimdShiftAcc",
"SimdSqrt",
@@ -1431,6 +1432,7 @@ class HPI_FloatSimdFU(MinorFU):
"SimdFloatMisc",
"SimdFloatMult",
"SimdFloatMultAcc",
"SimdFloatMatMultAcc",
"SimdFloatSqrt",
]
)