Minor fixes for full-system timing memory.

Need to rewrite bus bridge to get any further.

src/dev/io_device.cc:
    Set packet dest on timing responses.
src/mem/bus.cc:
    Fix dest addr bounds check assertion.
    Add assertion to catch infinite loopbacks.
src/mem/physical.cc:
    Add comment.

--HG--
extra : convert_revision : 419b65a3a61e2d099884dbda117b338dffd80896

src/dev/io_device.cc

@@ -78,6 +78,8 @@ bool
 PioPort::recvTiming(Packet *pkt)
 {
     device->recvAtomic(pkt);
+    // turn packet around to go back to requester
+    pkt->dest = pkt->src;
     sendTiming(pkt, pkt->time - pkt->req->getTime());
     return Success;
 }

src/mem/bus.cc

@@ -54,7 +54,8 @@ Bus::recvTiming(Packet *pkt)
     if (pkt->dest == Packet::Broadcast) {
         port = findPort(pkt->addr, pkt->src);
     } else {
-        assert(pkt->dest > 0 && pkt->dest < interfaces.size());
+        assert(pkt->dest >= 0 && pkt->dest < interfaces.size());
+        assert(pkt->dest != pkt->src); // catch infinite loops
         port = interfaces[pkt->dest];
     }
     return port->sendTiming(pkt);

src/mem/physical.cc

@@ -127,6 +127,7 @@ PhysicalMemory::doTimingAccess (Packet *pkt, MemoryPort* memoryPort)
 {
     doFunctionalAccess(pkt);
 
+    // turn packet around to go back to requester
     pkt->dest = pkt->src;
     MemResponseEvent* response = new MemResponseEvent(pkt, memoryPort);
     response->schedule(curTick + lat);