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arch-x86,cpu: Don't use aliases to hide TheISA::.

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We need to gradually eliminate TheISA, and so it's helpful to know where
it's actually being used. This change stops hiding it behind using-s
and, in one case, a placeholder constant.

Change-Id: I391a3129256a9f7bd3b4002d0a46fb06b3068468
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39656
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-01-24 21:43:45 -08:00
parent fb663678e6
commit ce20b07351
22 changed files with 268 additions and 291 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/x86/insts/static_inst.hh
View File

@@ -79,6 +79,8 @@ namespace X86ISA
class X86StaticInst : public StaticInst
{
protected:
using ExtMachInst = X86ISA::ExtMachInst;
// Constructor.
X86StaticInst(const char *mnem,
ExtMachInst _machInst, OpClass __opClass)

7
src/cpu/base_dyn_inst.hh
View File

@@ -79,7 +79,6 @@ class BaseDynInst : public ExecContext, public RefCounted
// Typedef for the CPU.
typedef typename Impl::CPUType ImplCPU;
typedef typename ImplCPU::ImplState ImplState;
using VecRegContainer = TheISA::VecRegContainer;
using LSQRequestPtr = typename Impl::CPUPol::LSQ::LSQRequest*;
using LQIterator = typename Impl::CPUPol::LSQUnit::LQIterator;
@@ -756,7 +755,7 @@ class BaseDynInst : public ExecContext, public RefCounted
/** Record a vector register being set to a value */
void
setVecRegOperand(const StaticInst *si, int idx,
const VecRegContainer &val) override
const TheISA::VecRegContainer &val) override
{
setVecResult(val);
}
@@ -771,7 +770,7 @@ class BaseDynInst : public ExecContext, public RefCounted
/** Record a vector register being set to a value */
void
setVecElemOperand(const StaticInst *si, int idx,
const VecElem val) override
const TheISA::VecElem val) override
{
setVecElemResult(val);
}
@@ -779,7 +778,7 @@ class BaseDynInst : public ExecContext, public RefCounted
/** Record a vector register being set to a value */
void
setVecPredRegOperand(const StaticInst *si, int idx,
const VecPredRegContainer &val) override
const TheISA::VecPredRegContainer &val) override
{
setVecPredResult(val);
}

20
src/cpu/checker/cpu.hh
View File

@@ -85,11 +85,9 @@ class Request;
class CheckerCPU : public BaseCPU, public ExecContext
{
protected:
typedef TheISA::MachInst MachInst;
using VecRegContainer = TheISA::VecRegContainer;
/** id attached to all issued requests */
RequestorID requestorId;
public:
void init() override;
@@ -201,7 +199,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
/**
* Read source vector register operand.
*/
const VecRegContainer &
const TheISA::VecRegContainer &
readVecRegOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->srcRegIdx(idx);
@@ -212,7 +210,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
/**
* Read destination vector register operand for modification.
*/
VecRegContainer &
TheISA::VecRegContainer &
getWritableVecRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->destRegIdx(idx);
@@ -293,14 +291,14 @@ class CheckerCPU : public BaseCPU, public ExecContext
}
/** @} */
VecElem
TheISA::VecElem
readVecElemOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->srcRegIdx(idx);
return thread->readVecElem(reg);
}
const VecPredRegContainer&
const TheISA::VecPredRegContainer&
readVecPredRegOperand(const StaticInst *si, int idx) const override
{
const RegId& reg = si->srcRegIdx(idx);
@@ -308,7 +306,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
return thread->readVecPredReg(reg);
}
VecPredRegContainer&
TheISA::VecPredRegContainer&
getWritableVecPredRegOperand(const StaticInst *si, int idx) override
{
const RegId& reg = si->destRegIdx(idx);
@@ -385,7 +383,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
void
setVecRegOperand(const StaticInst *si, int idx,
const VecRegContainer& val) override
const TheISA::VecRegContainer& val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecReg());
@@ -395,7 +393,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
void
setVecElemOperand(const StaticInst *si, int idx,
const VecElem val) override
const TheISA::VecElem val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecElem());
@@ -404,7 +402,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
}
void setVecPredRegOperand(const StaticInst *si, int idx,
const VecPredRegContainer& val) override
const TheISA::VecPredRegContainer& val) override
{
const RegId& reg = si->destRegIdx(idx);
assert(reg.isVecPredReg());

8
src/cpu/checker/cpu_impl.hh
View File

@@ -228,16 +228,16 @@ Checker<Impl>::verify(const DynInstPtr &completed_inst)
Addr fetch_PC = thread->instAddr();
fetch_PC = (fetch_PC & PCMask) + fetchOffset;
MachInst machInst;
TheISA::MachInst machInst;
// If not in the middle of a macro instruction
if (!curMacroStaticInst) {
// set up memory request for instruction fetch
auto mem_req = std::make_shared<Request>(
fetch_PC, sizeof(MachInst), 0, requestorId, fetch_PC,
thread->contextId());
fetch_PC, sizeof(TheISA::MachInst), 0, requestorId,
fetch_PC, thread->contextId());
mem_req->setVirt(fetch_PC, sizeof(MachInst),
mem_req->setVirt(fetch_PC, sizeof(TheISA::MachInst),
Request::INST_FETCH, requestorId,
thread->instAddr());

36
src/cpu/checker/thread_context.hh
View File

@@ -234,7 +234,7 @@ class CheckerThreadContext : public ThreadContext
return actualTC->readFloatReg(reg_idx);
}
const VecRegContainer &
const TheISA::VecRegContainer &
readVecReg (const RegId &reg) const override
{
return actualTC->readVecReg(reg);
@@ -243,7 +243,7 @@ class CheckerThreadContext : public ThreadContext
/**
* Read vector register for modification, hierarchical indexing.
*/
VecRegContainer &
TheISA::VecRegContainer &
getWritableVecReg (const RegId &reg) override
{
return actualTC->getWritableVecReg(reg);
@@ -306,19 +306,19 @@ class CheckerThreadContext : public ThreadContext
}
/** @} */
const VecElem &
const TheISA::VecElem &
readVecElem(const RegId& reg) const override
{
return actualTC->readVecElem(reg);
}
const VecPredRegContainer &
const TheISA::VecPredRegContainer &
readVecPredReg(const RegId& reg) const override
{
return actualTC->readVecPredReg(reg);
}
VecPredRegContainer &
TheISA::VecPredRegContainer &
getWritableVecPredReg(const RegId& reg) override
{
return actualTC->getWritableVecPredReg(reg);
@@ -345,21 +345,22 @@ class CheckerThreadContext : public ThreadContext
}
void
setVecReg(const RegId& reg, const VecRegContainer& val) override
setVecReg(const RegId& reg, const TheISA::VecRegContainer& val) override
{
actualTC->setVecReg(reg, val);
checkerTC->setVecReg(reg, val);
}
void
setVecElem(const RegId& reg, const VecElem& val) override
setVecElem(const RegId& reg, const TheISA::VecElem& val) override
{
actualTC->setVecElem(reg, val);
checkerTC->setVecElem(reg, val);
}
void
setVecPredReg(const RegId& reg, const VecPredRegContainer& val) override
setVecPredReg(const RegId& reg,
const TheISA::VecPredRegContainer& val) override
{
actualTC->setVecPredReg(reg, val);
checkerTC->setVecPredReg(reg, val);
@@ -486,7 +487,7 @@ class CheckerThreadContext : public ThreadContext
actualTC->setFloatRegFlat(idx, val);
}
const VecRegContainer &
const TheISA::VecRegContainer &
readVecRegFlat(RegIndex idx) const override
{
return actualTC->readVecRegFlat(idx);
@@ -495,45 +496,46 @@ class CheckerThreadContext : public ThreadContext
/**
* Read vector register for modification, flat indexing.
*/
VecRegContainer &
TheISA::VecRegContainer &
getWritableVecRegFlat(RegIndex idx) override
{
return actualTC->getWritableVecRegFlat(idx);
}
void
setVecRegFlat(RegIndex idx, const VecRegContainer& val) override
setVecRegFlat(RegIndex idx, const TheISA::VecRegContainer& val) override
{
actualTC->setVecRegFlat(idx, val);
}
const VecElem &
const TheISA::VecElem &
readVecElemFlat(RegIndex idx, const ElemIndex& elem_idx) const override
{
return actualTC->readVecElemFlat(idx, elem_idx);
}
void
setVecElemFlat(RegIndex idx,
const ElemIndex& elem_idx, const VecElem& val) override
setVecElemFlat(RegIndex idx, const ElemIndex& elem_idx,
const TheISA::VecElem& val) override
{
actualTC->setVecElemFlat(idx, elem_idx, val);
}
const VecPredRegContainer &
const TheISA::VecPredRegContainer &
readVecPredRegFlat(RegIndex idx) const override
{
return actualTC->readVecPredRegFlat(idx);
}
VecPredRegContainer &
TheISA::VecPredRegContainer &
getWritableVecPredRegFlat(RegIndex idx) override
{
return actualTC->getWritableVecPredRegFlat(idx);
}
void
setVecPredRegFlat(RegIndex idx, const VecPredRegContainer& val) override
setVecPredRegFlat(RegIndex idx,
const TheISA::VecPredRegContainer& val) override
{
actualTC->setVecPredRegFlat(idx, val);
}

42
src/cpu/exec_context.hh
View File

@@ -67,14 +67,8 @@
* implementation doesn't copy the pointer into any long-term storage
* (which is pretty hard to imagine they would have reason to do).
*/
class ExecContext {
public:
typedef TheISA::PCState PCState;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
using VecPredRegContainer = TheISA::VecPredRegContainer;
class ExecContext
{
public:
/**
* @{
@@ -111,17 +105,17 @@ class ExecContext {
/** Vector Register Interfaces. */
/** @{ */
/** Reads source vector register operand. */
virtual const VecRegContainer&
virtual const TheISA::VecRegContainer&
readVecRegOperand(const StaticInst *si, int idx) const = 0;
/** Gets destination vector register operand for modification. */
virtual VecRegContainer&
virtual TheISA::VecRegContainer&
getWritableVecRegOperand(const StaticInst *si, int idx) = 0;
/** Sets a destination vector register operand to a value. */
virtual void
setVecRegOperand(const StaticInst *si, int idx,
const VecRegContainer& val) = 0;
const TheISA::VecRegContainer& val) = 0;
/** @} */
/** Vector Register Lane Interfaces. */
@@ -157,28 +151,28 @@ class ExecContext {
/** Vector Elem Interfaces. */
/** @{ */
/** Reads an element of a vector register. */
virtual VecElem readVecElemOperand(const StaticInst *si,
int idx) const = 0;
virtual TheISA::VecElem readVecElemOperand(
const StaticInst *si, int idx) const = 0;
/** Sets a vector register to a value. */
virtual void setVecElemOperand(const StaticInst *si, int idx,
const VecElem val) = 0;
virtual void setVecElemOperand(
const StaticInst *si, int idx, const TheISA::VecElem val) = 0;
/** @} */
/** Predicate registers interface. */
/** @{ */
/** Reads source predicate register operand. */
virtual const VecPredRegContainer&
readVecPredRegOperand(const StaticInst *si, int idx) const = 0;
virtual const TheISA::VecPredRegContainer& readVecPredRegOperand(
const StaticInst *si, int idx) const = 0;
/** Gets destination predicate register operand for modification. */
virtual VecPredRegContainer&
getWritableVecPredRegOperand(const StaticInst *si, int idx) = 0;
virtual TheISA::VecPredRegContainer& getWritableVecPredRegOperand(
const StaticInst *si, int idx) = 0;
/** Sets a destination predicate register operand to a value. */
virtual void
setVecPredRegOperand(const StaticInst *si, int idx,
const VecPredRegContainer& val) = 0;
virtual void setVecPredRegOperand(
const StaticInst *si, int idx,
const TheISA::VecPredRegContainer& val) = 0;
/** @} */
/**
@@ -216,8 +210,8 @@ class ExecContext {
* @{
* @name PC Control
*/
virtual PCState pcState() const = 0;
virtual void pcState(const PCState &val) = 0;
virtual TheISA::PCState pcState() const = 0;
virtual void pcState(const TheISA::PCState &val) = 0;
/** @} */
/**

23
src/cpu/inst_res.hh
View File

@@ -43,17 +43,15 @@
#include "arch/generic/types.hh"
#include "arch/generic/vec_reg.hh"
class InstResult {
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
using VecPredRegContainer = TheISA::VecPredRegContainer;
class InstResult
{
public:
union MultiResult {
uint64_t integer;
double dbl;
VecRegContainer vector;
VecElem vecElem;
VecPredRegContainer pred;
TheISA::VecRegContainer vector;
TheISA::VecElem vecElem;
TheISA::VecPredRegContainer pred;
MultiResult() {}
};
@@ -87,10 +85,11 @@ class InstResult {
}
}
/** Vector result. */
explicit InstResult(const VecRegContainer& v, const ResultType& t)
explicit InstResult(const TheISA::VecRegContainer& v, const ResultType& t)
: type(t) { result.vector = v; }
/** Predicate result. */
explicit InstResult(const VecPredRegContainer& v, const ResultType& t)
explicit InstResult(const TheISA::VecPredRegContainer& v,
const ResultType& t)
: type(t) { result.pred = v; }
InstResult& operator=(const InstResult& that) {
@@ -178,20 +177,20 @@ class InstResult {
{
return result.integer;
}
const VecRegContainer&
const TheISA::VecRegContainer&
asVector() const
{
panic_if(!isVector(), "Converting scalar (or invalid) to vector!!");
return result.vector;
}
const VecElem&
const TheISA::VecElem&
asVectorElem() const
{
panic_if(!isVecElem(), "Converting scalar (or invalid) to vector!!");
return result.vecElem;
}
const VecPredRegContainer&
const TheISA::VecPredRegContainer&
asPred() const
{
panic_if(!isPred(), "Converting scalar (or invalid) to predicate!!");

51
src/cpu/o3/cpu.cc
View File

@@ -1182,44 +1182,40 @@ FullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg)
}
template <class Impl>
auto
const TheISA::VecRegContainer&
FullO3CPU<Impl>::readVecReg(PhysRegIdPtr phys_reg) const
-> const VecRegContainer&
{
cpuStats.vecRegfileReads++;
return regFile.readVecReg(phys_reg);
}
template <class Impl>
auto
TheISA::VecRegContainer&
FullO3CPU<Impl>::getWritableVecReg(PhysRegIdPtr phys_reg)
-> VecRegContainer&
{
cpuStats.vecRegfileWrites++;
return regFile.getWritableVecReg(phys_reg);
}
template <class Impl>
auto
FullO3CPU<Impl>::readVecElem(PhysRegIdPtr phys_reg) const -> const VecElem&
const TheISA::VecElem&
FullO3CPU<Impl>::readVecElem(PhysRegIdPtr phys_reg) const
{
cpuStats.vecRegfileReads++;
return regFile.readVecElem(phys_reg);
}
template <class Impl>
auto
const TheISA::VecPredRegContainer&
FullO3CPU<Impl>::readVecPredReg(PhysRegIdPtr phys_reg) const
-> const VecPredRegContainer&
{
cpuStats.vecPredRegfileReads++;
return regFile.readVecPredReg(phys_reg);
}
template <class Impl>
auto
TheISA::VecPredRegContainer&
FullO3CPU<Impl>::getWritableVecPredReg(PhysRegIdPtr phys_reg)
-> VecPredRegContainer&
{
cpuStats.vecPredRegfileWrites++;
return regFile.getWritableVecPredReg(phys_reg);
@@ -1251,7 +1247,8 @@ FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
template <class Impl>
void
FullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
FullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg,
const TheISA::VecRegContainer& val)
{
cpuStats.vecRegfileWrites++;
regFile.setVecReg(phys_reg, val);
@@ -1259,7 +1256,7 @@ FullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
template <class Impl>
void
FullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const VecElem& val)
FullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const TheISA::VecElem& val)
{
cpuStats.vecRegfileWrites++;
regFile.setVecElem(phys_reg, val);
@@ -1268,7 +1265,7 @@ FullO3CPU<Impl>::setVecElem(PhysRegIdPtr phys_reg, const VecElem& val)
template <class Impl>
void
FullO3CPU<Impl>::setVecPredReg(PhysRegIdPtr phys_reg,
const VecPredRegContainer& val)
const TheISA::VecPredRegContainer& val)
{
cpuStats.vecPredRegfileWrites++;
regFile.setVecPredReg(phys_reg, val);
@@ -1305,9 +1302,8 @@ FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
}
template <class Impl>
auto
const TheISA::VecRegContainer&
FullO3CPU<Impl>::readArchVecReg(int reg_idx, ThreadID tid) const
-> const VecRegContainer&
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecRegClass, reg_idx));
@@ -1315,9 +1311,8 @@ FullO3CPU<Impl>::readArchVecReg(int reg_idx, ThreadID tid) const
}
template <class Impl>
auto
TheISA::VecRegContainer&
FullO3CPU<Impl>::getWritableArchVecReg(int reg_idx, ThreadID tid)
-> VecRegContainer&
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecRegClass, reg_idx));
@@ -1325,9 +1320,9 @@ FullO3CPU<Impl>::getWritableArchVecReg(int reg_idx, ThreadID tid)
}
template <class Impl>
auto
FullO3CPU<Impl>::readArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
ThreadID tid) const -> const VecElem&
const TheISA::VecElem&
FullO3CPU<Impl>::readArchVecElem(
const RegIndex& reg_idx, const ElemIndex& ldx, ThreadID tid) const
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecElemClass, reg_idx, ldx));
@@ -1335,9 +1330,8 @@ FullO3CPU<Impl>::readArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
}
template <class Impl>
auto
const TheISA::VecPredRegContainer&
FullO3CPU<Impl>::readArchVecPredReg(int reg_idx, ThreadID tid) const
-> const VecPredRegContainer&
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecPredRegClass, reg_idx));
@@ -1345,9 +1339,8 @@ FullO3CPU<Impl>::readArchVecPredReg(int reg_idx, ThreadID tid) const
}
template <class Impl>
auto
TheISA::VecPredRegContainer&
FullO3CPU<Impl>::getWritableArchVecPredReg(int reg_idx, ThreadID tid)
-> VecPredRegContainer&
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecPredRegClass, reg_idx));
@@ -1389,8 +1382,8 @@ FullO3CPU<Impl>::setArchFloatReg(int reg_idx, RegVal val, ThreadID tid)
template <class Impl>
void
FullO3CPU<Impl>::setArchVecReg(int reg_idx, const VecRegContainer& val,
ThreadID tid)
FullO3CPU<Impl>::setArchVecReg(int reg_idx,
const TheISA::VecRegContainer& val, ThreadID tid)
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecRegClass, reg_idx));
@@ -1400,7 +1393,7 @@ FullO3CPU<Impl>::setArchVecReg(int reg_idx, const VecRegContainer& val,
template <class Impl>
void
FullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
const VecElem& val, ThreadID tid)
const TheISA::VecElem& val, ThreadID tid)
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecElemClass, reg_idx, ldx));
@@ -1409,8 +1402,8 @@ FullO3CPU<Impl>::setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
template <class Impl>
void
FullO3CPU<Impl>::setArchVecPredReg(int reg_idx, const VecPredRegContainer& val,
ThreadID tid)
FullO3CPU<Impl>::setArchVecPredReg(int reg_idx,
const TheISA::VecPredRegContainer& val, ThreadID tid)
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecPredRegClass, reg_idx));

64
src/cpu/o3/cpu.hh
View File

@@ -96,11 +96,6 @@ class FullO3CPU : public BaseO3CPU
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::O3CPU O3CPU;
using VecElem = TheISA::VecElem;
using VecRegContainer = TheISA::VecRegContainer;
using VecPredRegContainer = TheISA::VecPredRegContainer;
typedef O3ThreadState<Impl> ImplState;
typedef O3ThreadState<Impl> Thread;
@@ -336,12 +331,12 @@ class FullO3CPU : public BaseO3CPU
RegVal readFloatReg(PhysRegIdPtr phys_reg);
const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;
const TheISA::VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;
/**
* Read physical vector register for modification.
*/
VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx);
TheISA::VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx);
/** Returns current vector renaming mode */
Enums::VecRegRenameMode vecRenameMode() const { return vecMode; }
@@ -353,23 +348,23 @@ class FullO3CPU : public BaseO3CPU
/**
* Read physical vector register lane
*/
template<typename VecElem, int LaneIdx>
VecLaneT<VecElem, true>
template<typename VE, int LaneIdx>
VecLaneT<VE, true>
readVecLane(PhysRegIdPtr phys_reg) const
{
cpuStats.vecRegfileReads++;
return regFile.readVecLane<VecElem, LaneIdx>(phys_reg);
return regFile.readVecLane<VE, LaneIdx>(phys_reg);
}
/**
* Read physical vector register lane
*/
template<typename VecElem>
VecLaneT<VecElem, true>
template<typename VE>
VecLaneT<VE, true>
readVecLane(PhysRegIdPtr phys_reg) const
{
cpuStats.vecRegfileReads++;
return regFile.readVecLane<VecElem>(phys_reg);
return regFile.readVecLane<VE>(phys_reg);
}
/** Write a lane of the destination vector register. */
@@ -381,11 +376,12 @@ class FullO3CPU : public BaseO3CPU
return regFile.setVecLane(phys_reg, val);
}
const VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
const TheISA::VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
const VecPredRegContainer& readVecPredReg(PhysRegIdPtr reg_idx) const;
const TheISA::VecPredRegContainer&
readVecPredReg(PhysRegIdPtr reg_idx) const;
VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx);
TheISA::VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx);
RegVal readCCReg(PhysRegIdPtr phys_reg);
@@ -393,11 +389,12 @@ class FullO3CPU : public BaseO3CPU
void setFloatReg(PhysRegIdPtr phys_reg, RegVal val);
void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val);
void setVecReg(PhysRegIdPtr reg_idx, const TheISA::VecRegContainer& val);
void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val);
void setVecElem(PhysRegIdPtr reg_idx, const TheISA::VecElem& val);
void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val);
void setVecPredReg(PhysRegIdPtr reg_idx,
const TheISA::VecPredRegContainer& val);
void setCCReg(PhysRegIdPtr phys_reg, RegVal val);
@@ -405,18 +402,19 @@ class FullO3CPU : public BaseO3CPU
RegVal readArchFloatReg(int reg_idx, ThreadID tid);
const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const;
const TheISA::VecRegContainer&
readArchVecReg(int reg_idx, ThreadID tid) const;
/** Read architectural vector register for modification. */
VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid);
TheISA::VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid);
/** Read architectural vector register lane. */
template<typename VecElem>
VecLaneT<VecElem, true>
template<typename VE>
VecLaneT<VE, true>
readArchVecLane(int reg_idx, int lId, ThreadID tid) const
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecRegClass, reg_idx));
return readVecLane<VecElem>(phys_reg);
return readVecLane<VE>(phys_reg);
}
@@ -430,13 +428,14 @@ class FullO3CPU : public BaseO3CPU
setVecLane(phys_reg, val);
}
const VecElem& readArchVecElem(const RegIndex& reg_idx,
const ElemIndex& ldx, ThreadID tid) const;
const TheISA::VecElem& readArchVecElem(const RegIndex& reg_idx,
const ElemIndex& ldx, ThreadID tid) const;
const VecPredRegContainer& readArchVecPredReg(int reg_idx,
ThreadID tid) const;
const TheISA::VecPredRegContainer& readArchVecPredReg(
int reg_idx, ThreadID tid) const;
VecPredRegContainer& getWritableArchVecPredReg(int reg_idx, ThreadID tid);
TheISA::VecPredRegContainer&
getWritableArchVecPredReg(int reg_idx, ThreadID tid);
RegVal readArchCCReg(int reg_idx, ThreadID tid);
@@ -449,13 +448,14 @@ class FullO3CPU : public BaseO3CPU
void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid);
void setArchVecPredReg(int reg_idx, const VecPredRegContainer& val,
void setArchVecPredReg(int reg_idx, const TheISA::VecPredRegContainer& val,
ThreadID tid);
void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid);
void setArchVecReg(int reg_idx, const TheISA::VecRegContainer& val,
ThreadID tid);
void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
const VecElem& val, ThreadID tid);
const TheISA::VecElem& val, ThreadID tid);
void setArchCCReg(int reg_idx, RegVal val, ThreadID tid);

25
src/cpu/o3/dyn_inst.hh
View File

@@ -60,13 +60,8 @@ class BaseO3DynInst : public BaseDynInst<Impl>
/** Typedef for the CPU. */
typedef typename Impl::O3CPU O3CPU;
/** Binary machine instruction type. */
typedef TheISA::MachInst MachInst;
/** Register types. */
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
using VecPredRegContainer = TheISA::VecPredRegContainer;
enum {
MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
@@ -273,7 +268,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
}
const VecRegContainer&
const TheISA::VecRegContainer&
readVecRegOperand(const StaticInst *si, int idx) const override
{
return this->cpu->readVecReg(this->_srcRegIdx[idx]);
@@ -282,7 +277,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
/**
* Read destination vector register operand for modification.
*/
VecRegContainer&
TheISA::VecRegContainer&
getWritableVecRegOperand(const StaticInst *si, int idx) override
{
return this->cpu->getWritableVecReg(this->_destRegIdx[idx]);
@@ -351,18 +346,19 @@ class BaseO3DynInst : public BaseDynInst<Impl>
}
/** @} */
VecElem readVecElemOperand(const StaticInst *si, int idx) const override
TheISA::VecElem
readVecElemOperand(const StaticInst *si, int idx) const override
{
return this->cpu->readVecElem(this->_srcRegIdx[idx]);
}
const VecPredRegContainer&
const TheISA::VecPredRegContainer&
readVecPredRegOperand(const StaticInst *si, int idx) const override
{
return this->cpu->readVecPredReg(this->_srcRegIdx[idx]);
}
VecPredRegContainer&
TheISA::VecPredRegContainer&
getWritableVecPredRegOperand(const StaticInst *si, int idx) override
{
return this->cpu->getWritableVecPredReg(this->_destRegIdx[idx]);
@@ -393,14 +389,15 @@ class BaseO3DynInst : public BaseDynInst<Impl>
void
setVecRegOperand(const StaticInst *si, int idx,
const VecRegContainer& val) override
const TheISA::VecRegContainer& val) override
{
this->cpu->setVecReg(this->_destRegIdx[idx], val);
BaseDynInst<Impl>::setVecRegOperand(si, idx, val);
}
void setVecElemOperand(const StaticInst *si, int idx,
const VecElem val) override
void
setVecElemOperand(const StaticInst *si, int idx,
const TheISA::VecElem val) override
{
int reg_idx = idx;
this->cpu->setVecElem(this->_destRegIdx[reg_idx], val);
@@ -409,7 +406,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
void
setVecPredRegOperand(const StaticInst *si, int idx,
const VecPredRegContainer& val) override
const TheISA::VecPredRegContainer& val) override
{
this->cpu->setVecPredReg(this->_destRegIdx[idx], val);
BaseDynInst<Impl>::setVecPredRegOperand(si, idx, val);

3
src/cpu/o3/fetch.hh
View File

@@ -81,9 +81,6 @@ class DefaultFetch
typedef typename CPUPol::FetchStruct FetchStruct;
typedef typename CPUPol::TimeStruct TimeStruct;
/** Typedefs from ISA. */
typedef TheISA::MachInst MachInst;
/**
* IcachePort class for instruction fetch.
*/

3
src/cpu/o3/impl.hh
View File

@@ -49,9 +49,6 @@ class FullO3CPU;
*/
struct O3CPUImpl
{
/** The type of MachInst. */
typedef TheISA::MachInst MachInst;
/** The CPU policy to be used, which defines all of the CPU stages. */
typedef SimpleCPUPolicy<O3CPUImpl> CPUPol;

19
src/cpu/o3/regfile.cc
View File

@@ -60,13 +60,13 @@ PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs,
numPhysicalFloatRegs(_numPhysicalFloatRegs),
numPhysicalVecRegs(_numPhysicalVecRegs),
numPhysicalVecElemRegs(_numPhysicalVecRegs *
NumVecElemPerVecReg),
TheISA::NumVecElemPerVecReg),
numPhysicalVecPredRegs(_numPhysicalVecPredRegs),
numPhysicalCCRegs(_numPhysicalCCRegs),
totalNumRegs(_numPhysicalIntRegs
+ _numPhysicalFloatRegs
+ _numPhysicalVecRegs
+ _numPhysicalVecRegs * NumVecElemPerVecReg
+ _numPhysicalVecRegs * TheISA::NumVecElemPerVecReg
+ _numPhysicalVecPredRegs
+ _numPhysicalCCRegs),
vecMode(vmode)
@@ -102,7 +102,7 @@ PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs,
// registers, just a different (and incompatible) way to access
// them; put them onto the vector free list.
for (phys_reg = 0; phys_reg < numPhysicalVecRegs; phys_reg++) {
for (ElemIndex eIdx = 0; eIdx < NumVecElemPerVecReg; eIdx++) {
for (ElemIndex eIdx = 0; eIdx < TheISA::NumVecElemPerVecReg; eIdx++) {
vecElemIds.emplace_back(VecElemClass, phys_reg,
eIdx, flat_reg_idx++);
}
@@ -150,10 +150,11 @@ PhysRegFile::initFreeList(UnifiedFreeList *freeList)
* registers; put them onto the vector free list. */
for (reg_idx = 0; reg_idx < numPhysicalVecRegs; reg_idx++) {
assert(vecRegIds[reg_idx].index() == reg_idx);
for (ElemIndex elemIdx = 0; elemIdx < NumVecElemPerVecReg; elemIdx++) {
assert(vecElemIds[reg_idx * NumVecElemPerVecReg +
for (ElemIndex elemIdx = 0; elemIdx < TheISA::NumVecElemPerVecReg;
elemIdx++) {
assert(vecElemIds[reg_idx * TheISA::NumVecElemPerVecReg +
elemIdx].index() == reg_idx);
assert(vecElemIds[reg_idx * NumVecElemPerVecReg +
assert(vecElemIds[reg_idx * TheISA::NumVecElemPerVecReg +
elemIdx].elemIndex() == elemIdx);
}
}
@@ -187,8 +188,8 @@ PhysRegFile::getRegElemIds(PhysRegIdPtr reg)
"Trying to get elems of a %s register", reg->className());
auto idx = reg->index();
return std::make_pair(
vecElemIds.begin() + idx * NumVecElemPerVecReg,
vecElemIds.begin() + (idx+1) * NumVecElemPerVecReg);
vecElemIds.begin() + idx * TheISA::NumVecElemPerVecReg,
vecElemIds.begin() + (idx+1) * TheISA::NumVecElemPerVecReg);
}
PhysRegFile::IdRange
@@ -223,7 +224,7 @@ PhysRegFile::getTrueId(PhysRegIdPtr reg)
case VecRegClass:
return &vecRegIds[reg->index()];
case VecElemClass:
return &vecElemIds[reg->index() * NumVecElemPerVecReg +
return &vecElemIds[reg->index() * TheISA::NumVecElemPerVecReg +
reg->elemIndex()];
default:
panic_if(!reg->isVectorPhysElem(),

54
src/cpu/o3/regfile.hh
View File

@@ -60,17 +60,12 @@ class PhysRegFile
{
private:
using VecElem = TheISA::VecElem;
using VecRegContainer = TheISA::VecRegContainer;
using PhysIds = std::vector<PhysRegId>;
using VecMode = Enums::VecRegRenameMode;
using VecPredRegContainer = TheISA::VecPredRegContainer;
public:
using IdRange = std::pair<PhysIds::iterator,
PhysIds::iterator>;
private:
static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg;
/** Integer register file. */
std::vector<RegVal> intRegFile;
std::vector<PhysRegId> intRegIds;
@@ -80,12 +75,12 @@ class PhysRegFile
std::vector<PhysRegId> floatRegIds;
/** Vector register file. */
std::vector<VecRegContainer> vectorRegFile;
std::vector<TheISA::VecRegContainer> vectorRegFile;
std::vector<PhysRegId> vecRegIds;
std::vector<PhysRegId> vecElemIds;
/** Predicate register file. */
std::vector<VecPredRegContainer> vecPredRegFile;
std::vector<TheISA::VecPredRegContainer> vecPredRegFile;
std::vector<PhysRegId> vecPredRegIds;
/** Condition-code register file. */
@@ -201,7 +196,7 @@ class PhysRegFile
}
/** Reads a vector register. */
const VecRegContainer &
const TheISA::VecRegContainer &
readVecReg(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->isVectorPhysReg());
@@ -214,27 +209,27 @@ class PhysRegFile
}
/** Reads a vector register for modification. */
VecRegContainer &
TheISA::VecRegContainer &
getWritableVecReg(PhysRegIdPtr phys_reg)
{
/* const_cast for not duplicating code above. */
return const_cast<VecRegContainer&>(readVecReg(phys_reg));
return const_cast<TheISA::VecRegContainer&>(readVecReg(phys_reg));
}
/** Reads a vector register lane. */
template <typename VecElem, int LaneIdx>
VecLaneT<VecElem, true>
template <typename VE, int LaneIdx>
VecLaneT<VE, true>
readVecLane(PhysRegIdPtr phys_reg) const
{
return readVecReg(phys_reg).laneView<VecElem, LaneIdx>();
return readVecReg(phys_reg).laneView<VE, LaneIdx>();
}
/** Reads a vector register lane. */
template <typename VecElem>
VecLaneT<VecElem, true>
template <typename VE>
VecLaneT<VE, true>
readVecLane(PhysRegIdPtr phys_reg) const
{
return readVecReg(phys_reg).laneView<VecElem>(phys_reg->elemIndex());
return readVecReg(phys_reg).laneView<VE>(phys_reg->elemIndex());
}
/** Get a vector register lane for modification. */
@@ -252,12 +247,12 @@ class PhysRegFile
}
/** Reads a vector element. */
const VecElem &
const TheISA::VecElem &
readVecElem(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->isVectorPhysElem());
auto ret = vectorRegFile[phys_reg->index()].as<VecElem>();
const VecElem& val = ret[phys_reg->elemIndex()];
auto ret = vectorRegFile[phys_reg->index()].as<TheISA::VecElem>();
const TheISA::VecElem& val = ret[phys_reg->elemIndex()];
DPRINTF(IEW, "RegFile: Access to element %d of vector register %i,"
" has data %#x\n", phys_reg->elemIndex(),
int(phys_reg->index()), val);
@@ -266,7 +261,8 @@ class PhysRegFile
}
/** Reads a predicate register. */
const VecPredRegContainer& readVecPredReg(PhysRegIdPtr phys_reg) const
const TheISA::VecPredRegContainer&
readVecPredReg(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->isVecPredPhysReg());
@@ -277,10 +273,12 @@ class PhysRegFile
return vecPredRegFile[phys_reg->index()];
}
VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr phys_reg)
TheISA::VecPredRegContainer&
getWritableVecPredReg(PhysRegIdPtr phys_reg)
{
/* const_cast for not duplicating code above. */
return const_cast<VecPredRegContainer&>(readVecPredReg(phys_reg));
return const_cast<TheISA::VecPredRegContainer&>(
readVecPredReg(phys_reg));
}
/** Reads a condition-code register. */
@@ -323,7 +321,7 @@ class PhysRegFile
/** Sets a vector register to the given value. */
void
setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val)
setVecReg(PhysRegIdPtr phys_reg, const TheISA::VecRegContainer& val)
{
assert(phys_reg->isVectorPhysReg());
@@ -335,19 +333,21 @@ class PhysRegFile
/** Sets a vector register to the given value. */
void
setVecElem(PhysRegIdPtr phys_reg, const VecElem val)
setVecElem(PhysRegIdPtr phys_reg, const TheISA::VecElem val)
{
assert(phys_reg->isVectorPhysElem());
DPRINTF(IEW, "RegFile: Setting element %d of vector register %i to"
" %#x\n", phys_reg->elemIndex(), int(phys_reg->index()), val);
vectorRegFile[phys_reg->index()].as<VecElem>()[phys_reg->elemIndex()] =
val;
vectorRegFile[phys_reg->index()].as<TheISA::VecElem>()[
phys_reg->elemIndex()] = val;
}
/** Sets a predicate register to the given value. */
void setVecPredReg(PhysRegIdPtr phys_reg, const VecPredRegContainer& val)
void
setVecPredReg(PhysRegIdPtr phys_reg,
const TheISA::VecPredRegContainer& val)
{
assert(phys_reg->isVecPredPhysReg());

6
src/cpu/o3/rename_map.cc
View File

@@ -120,7 +120,7 @@ UnifiedRenameMap::init(PhysRegFile *_regFile,
vecMap.init(TheISA::NumVecRegs, &(freeList->vecList), (RegIndex)-1);
vecElemMap.init(TheISA::NumVecRegs * NVecElems,
vecElemMap.init(TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg,
&(freeList->vecElemList), (RegIndex)-1);
predMap.init(TheISA::NumVecPredRegs, &(freeList->predList), (RegIndex)-1);
@@ -200,8 +200,8 @@ UnifiedRenameMap::switchMode(VecMode newVecMode)
*/
TheISA::VecRegContainer new_RF[TheISA::NumVecRegs];
for (uint32_t i = 0; i < TheISA::NumVecRegs; i++) {
VecReg dst = new_RF[i].as<TheISA::VecElem>();
for (uint32_t l = 0; l < NVecElems; l++) {
TheISA::VecReg dst = new_RF[i].as<TheISA::VecElem>();
for (uint32_t l = 0; l < TheISA::NumVecElemPerVecReg; l++) {
RegId s_rid(VecElemClass, i, l);
PhysRegIdPtr s_prid = vecElemMap.lookup(s_rid);
dst[l] = regFile->readVecElem(s_prid);

4
src/cpu/o3/rename_map.hh
View File

@@ -169,10 +169,6 @@ class SimpleRenameMap
class UnifiedRenameMap
{
private:
static constexpr uint32_t NVecElems = TheISA::NumVecElemPerVecReg;
using VecReg = TheISA::VecReg;
using VecPredReg = TheISA::VecPredReg;
/** The integer register rename map */
SimpleRenameMap intMap;

43
src/cpu/o3/thread_context.hh
View File

@@ -204,7 +204,7 @@ class O3ThreadContext : public ThreadContext
reg_idx)).index());
}
const VecRegContainer &
const TheISA::VecRegContainer &
readVecReg(const RegId& id) const override
{
return readVecRegFlat(flattenRegId(id).index());
@@ -213,7 +213,7 @@ class O3ThreadContext : public ThreadContext
/**
* Read vector register operand for modification, hierarchical indexing.
*/
VecRegContainer &
TheISA::VecRegContainer &
getWritableVecReg(const RegId& id) override
{
return getWritableVecRegFlat(flattenRegId(id).index());
@@ -280,19 +280,19 @@ class O3ThreadContext : public ThreadContext
}
/** @} */
const VecElem &
const TheISA::VecElem &
readVecElem(const RegId& reg) const override
{
return readVecElemFlat(flattenRegId(reg).index(), reg.elemIndex());
}
const VecPredRegContainer &
const TheISA::VecPredRegContainer &
readVecPredReg(const RegId& id) const override
{
return readVecPredRegFlat(flattenRegId(id).index());
}
VecPredRegContainer&
TheISA::VecPredRegContainer&
getWritableVecPredReg(const RegId& id) override
{
return getWritableVecPredRegFlat(flattenRegId(id).index());
@@ -320,20 +320,20 @@ class O3ThreadContext : public ThreadContext
}
void
setVecReg(const RegId& reg, const VecRegContainer& val) override
setVecReg(const RegId& reg, const TheISA::VecRegContainer& val) override
{
setVecRegFlat(flattenRegId(reg).index(), val);
}
void
setVecElem(const RegId& reg, const VecElem& val) override
setVecElem(const RegId& reg, const TheISA::VecElem& val) override
{
setVecElemFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
}
void
setVecPredReg(const RegId& reg,
const VecPredRegContainer& val) override
const TheISA::VecPredRegContainer& val) override
{
setVecPredRegFlat(flattenRegId(reg).index(), val);
}
@@ -437,16 +437,17 @@ class O3ThreadContext : public ThreadContext
RegVal readFloatRegFlat(RegIndex idx) const override;
void setFloatRegFlat(RegIndex idx, RegVal val) override;
const VecRegContainer& readVecRegFlat(RegIndex idx) const override;
const TheISA::VecRegContainer& readVecRegFlat(RegIndex idx) const override;
/** Read vector register operand for modification, flat indexing. */
VecRegContainer& getWritableVecRegFlat(RegIndex idx) override;
void setVecRegFlat(RegIndex idx, const VecRegContainer& val) override;
TheISA::VecRegContainer& getWritableVecRegFlat(RegIndex idx) override;
void setVecRegFlat(RegIndex idx,
const TheISA::VecRegContainer& val) override;
template <typename VecElem>
VecLaneT<VecElem, true>
template <typename VE>
VecLaneT<VE, true>
readVecLaneFlat(RegIndex idx, int lId) const
{
return cpu->template readArchVecLane<VecElem>(idx, lId,
return cpu->template readArchVecLane<VE>(idx, lId,
thread->threadId());
}
@@ -457,15 +458,17 @@ class O3ThreadContext : public ThreadContext
cpu->template setArchVecLane(idx, lId, thread->threadId(), val);
}
const VecElem &readVecElemFlat(RegIndex idx,
const ElemIndex& elemIndex) const override;
const TheISA::VecElem &readVecElemFlat(RegIndex idx,
const ElemIndex& elemIndex) const override;
void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
const VecElem& val) override;
const TheISA::VecElem& val) override;
const VecPredRegContainer& readVecPredRegFlat(RegIndex idx) const override;
VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) override;
const TheISA::VecPredRegContainer&
readVecPredRegFlat(RegIndex idx) const override;
TheISA::VecPredRegContainer&
getWritableVecPredRegFlat(RegIndex idx) override;
void setVecPredRegFlat(RegIndex idx,
const VecPredRegContainer& val) override;
const TheISA::VecPredRegContainer& val) override;
RegVal readCCRegFlat(RegIndex idx) const override;
void setCCRegFlat(RegIndex idx, RegVal val) override;

6
src/cpu/o3/thread_context_impl.hh
View File

@@ -247,7 +247,7 @@ O3ThreadContext<Impl>::setFloatRegFlat(RegIndex reg_idx, RegVal val)
template <class Impl>
void
O3ThreadContext<Impl>::setVecRegFlat(
RegIndex reg_idx, const VecRegContainer& val)
RegIndex reg_idx, const TheISA::VecRegContainer& val)
{
cpu->setArchVecReg(reg_idx, val, thread->threadId());
@@ -257,7 +257,7 @@ O3ThreadContext<Impl>::setVecRegFlat(
template <class Impl>
void
O3ThreadContext<Impl>::setVecElemFlat(RegIndex idx,
const ElemIndex& elemIndex, const VecElem& val)
const ElemIndex& elemIndex, const TheISA::VecElem& val)
{
cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
conditionalSquash();
@@ -266,7 +266,7 @@ O3ThreadContext<Impl>::setVecElemFlat(RegIndex idx,
template <class Impl>
void
O3ThreadContext<Impl>::setVecPredRegFlat(RegIndex reg_idx,
const VecPredRegContainer& val)
const TheISA::VecPredRegContainer& val)
{
cpu->setArchVecPredReg(reg_idx, val, thread->threadId());

33
src/cpu/simple/exec_context.hh
View File

@@ -54,11 +54,8 @@
class BaseSimpleCPU;
class SimpleExecContext : public ExecContext {
protected:
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
class SimpleExecContext : public ExecContext
{
public:
BaseSimpleCPU *cpu;
SimpleThread* thread;
@@ -304,7 +301,7 @@ class SimpleExecContext : public ExecContext {
}
/** Reads a vector register. */
const VecRegContainer &
const TheISA::VecRegContainer &
readVecRegOperand(const StaticInst *si, int idx) const override
{
execContextStats.numVecRegReads++;
@@ -314,7 +311,7 @@ class SimpleExecContext : public ExecContext {
}
/** Reads a vector register for modification. */
VecRegContainer &
TheISA::VecRegContainer &
getWritableVecRegOperand(const StaticInst *si, int idx) override
{
execContextStats.numVecRegWrites++;
@@ -326,7 +323,7 @@ class SimpleExecContext : public ExecContext {
/** Sets a vector register to a value. */
void
setVecRegOperand(const StaticInst *si, int idx,
const VecRegContainer& val) override
const TheISA::VecRegContainer& val) override
{
execContextStats.numVecRegWrites++;
const RegId& reg = si->destRegIdx(idx);
@@ -337,14 +334,14 @@ class SimpleExecContext : public ExecContext {
/** Vector Register Lane Interfaces. */
/** @{ */
/** Reads source vector lane. */
template <typename VecElem>
VecLaneT<VecElem, true>
template <typename VE>
VecLaneT<VE, true>
readVecLaneOperand(const StaticInst *si, int idx) const
{
execContextStats.numVecRegReads++;
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isVecReg());
return thread->readVecLane<VecElem>(reg);
return thread->readVecLane<VE>(reg);
}
/** Reads source vector 8bit operand. */
virtual ConstVecLane8
@@ -404,7 +401,7 @@ class SimpleExecContext : public ExecContext {
/** @} */
/** Reads an element of a vector register. */
VecElem
TheISA::VecElem
readVecElemOperand(const StaticInst *si, int idx) const override
{
execContextStats.numVecRegReads++;
@@ -416,7 +413,7 @@ class SimpleExecContext : public ExecContext {
/** Sets an element of a vector register to a value. */
void
setVecElemOperand(const StaticInst *si, int idx,
const VecElem val) override
const TheISA::VecElem val) override
{
execContextStats.numVecRegWrites++;
const RegId& reg = si->destRegIdx(idx);
@@ -424,7 +421,7 @@ class SimpleExecContext : public ExecContext {
thread->setVecElem(reg, val);
}
const VecPredRegContainer&
const TheISA::VecPredRegContainer&
readVecPredRegOperand(const StaticInst *si, int idx) const override
{
execContextStats.numVecPredRegReads++;
@@ -433,7 +430,7 @@ class SimpleExecContext : public ExecContext {
return thread->readVecPredReg(reg);
}
VecPredRegContainer&
TheISA::VecPredRegContainer&
getWritableVecPredRegOperand(const StaticInst *si, int idx) override
{
execContextStats.numVecPredRegWrites++;
@@ -444,7 +441,7 @@ class SimpleExecContext : public ExecContext {
void
setVecPredRegOperand(const StaticInst *si, int idx,
const VecPredRegContainer& val) override
const TheISA::VecPredRegContainer& val) override
{
execContextStats.numVecPredRegWrites++;
const RegId& reg = si->destRegIdx(idx);
@@ -510,14 +507,14 @@ class SimpleExecContext : public ExecContext {
thread->setMiscReg(misc_reg, val);
}
PCState
TheISA::PCState
pcState() const override
{
return thread->pcState();
}
void
pcState(const PCState &val) override
pcState(const TheISA::PCState &val) override
{
thread->pcState(val);
}

57
src/cpu/simple_thread.hh
View File

@@ -89,19 +89,15 @@ class CheckerCPU;
class SimpleThread : public ThreadState, public ThreadContext
{
protected:
typedef TheISA::MachInst MachInst;
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
using VecPredRegContainer = TheISA::VecPredRegContainer;
public:
typedef ThreadContext::Status Status;
protected:
std::array<RegVal, TheISA::NumFloatRegs> floatRegs;
std::array<RegVal, TheISA::NumIntRegs> intRegs;
std::array<VecRegContainer, TheISA::NumVecRegs> vecRegs;
std::array<VecPredRegContainer, TheISA::NumVecPredRegs> vecPredRegs;
std::array<TheISA::VecRegContainer, TheISA::NumVecRegs> vecRegs;
std::array<TheISA::VecPredRegContainer, TheISA::NumVecPredRegs>
vecPredRegs;
std::array<RegVal, TheISA::NumCCRegs> ccRegs;
TheISA::ISA *const isa; // one "instance" of the current ISA.
@@ -292,23 +288,23 @@ class SimpleThread : public ThreadState, public ThreadContext
return regVal;
}
const VecRegContainer&
const TheISA::VecRegContainer&
readVecReg(const RegId& reg) const override
{
int flatIndex = isa->flattenVecIndex(reg.index());
assert(flatIndex < TheISA::NumVecRegs);
const VecRegContainer& regVal = readVecRegFlat(flatIndex);
const TheISA::VecRegContainer& regVal = readVecRegFlat(flatIndex);
DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s.\n",
reg.index(), flatIndex, regVal.print());
return regVal;
}
VecRegContainer&
TheISA::VecRegContainer&
getWritableVecReg(const RegId& reg) override
{
int flatIndex = isa->flattenVecIndex(reg.index());
assert(flatIndex < TheISA::NumVecRegs);
VecRegContainer& regVal = getWritableVecRegFlat(flatIndex);
TheISA::VecRegContainer& regVal = getWritableVecRegFlat(flatIndex);
DPRINTF(VecRegs, "Reading vector reg %d (%d) as %s for modify.\n",
reg.index(), flatIndex, regVal.print());
return regVal;
@@ -393,34 +389,37 @@ class SimpleThread : public ThreadState, public ThreadContext
}
/** @} */
const VecElem &
const TheISA::VecElem &
readVecElem(const RegId &reg) const override
{
int flatIndex = isa->flattenVecElemIndex(reg.index());
assert(flatIndex < TheISA::NumVecRegs);
const VecElem& regVal = readVecElemFlat(flatIndex, reg.elemIndex());
const TheISA::VecElem& regVal =
readVecElemFlat(flatIndex, reg.elemIndex());
DPRINTF(VecRegs, "Reading element %d of vector reg %d (%d) as"
" %#x.\n", reg.elemIndex(), reg.index(), flatIndex, regVal);
return regVal;
}
const VecPredRegContainer &
const TheISA::VecPredRegContainer &
readVecPredReg(const RegId &reg) const override
{
int flatIndex = isa->flattenVecPredIndex(reg.index());
assert(flatIndex < TheISA::NumVecPredRegs);
const VecPredRegContainer& regVal = readVecPredRegFlat(flatIndex);
const TheISA::VecPredRegContainer& regVal =
readVecPredRegFlat(flatIndex);
DPRINTF(VecPredRegs, "Reading predicate reg %d (%d) as %s.\n",
reg.index(), flatIndex, regVal.print());
return regVal;
}
VecPredRegContainer &
TheISA::VecPredRegContainer &
getWritableVecPredReg(const RegId &reg) override
{
int flatIndex = isa->flattenVecPredIndex(reg.index());
assert(flatIndex < TheISA::NumVecPredRegs);
VecPredRegContainer& regVal = getWritableVecPredRegFlat(flatIndex);
TheISA::VecPredRegContainer& regVal =
getWritableVecPredRegFlat(flatIndex);
DPRINTF(VecPredRegs,
"Reading predicate reg %d (%d) as %s for modify.\n",
reg.index(), flatIndex, regVal.print());
@@ -463,7 +462,7 @@ class SimpleThread : public ThreadState, public ThreadContext
}
void
setVecReg(const RegId &reg, const VecRegContainer &val) override
setVecReg(const RegId &reg, const TheISA::VecRegContainer &val) override
{
int flatIndex = isa->flattenVecIndex(reg.index());
assert(flatIndex < TheISA::NumVecRegs);
@@ -473,7 +472,7 @@ class SimpleThread : public ThreadState, public ThreadContext
}
void
setVecElem(const RegId &reg, const VecElem &val) override
setVecElem(const RegId &reg, const TheISA::VecElem &val) override
{
int flatIndex = isa->flattenVecElemIndex(reg.index());
assert(flatIndex < TheISA::NumVecRegs);
@@ -483,7 +482,8 @@ class SimpleThread : public ThreadState, public ThreadContext
}
void
setVecPredReg(const RegId &reg, const VecPredRegContainer &val) override
setVecPredReg(const RegId &reg,
const TheISA::VecPredRegContainer &val) override
{
int flatIndex = isa->flattenVecPredIndex(reg.index());
assert(flatIndex < TheISA::NumVecPredRegs);
@@ -591,20 +591,20 @@ class SimpleThread : public ThreadState, public ThreadContext
floatRegs[idx] = val;
}
const VecRegContainer &
const TheISA::VecRegContainer &
readVecRegFlat(RegIndex reg) const override
{
return vecRegs[reg];
}
VecRegContainer &
TheISA::VecRegContainer &
getWritableVecRegFlat(RegIndex reg) override
{
return vecRegs[reg];
}
void
setVecRegFlat(RegIndex reg, const VecRegContainer &val) override
setVecRegFlat(RegIndex reg, const TheISA::VecRegContainer &val) override
{
vecRegs[reg] = val;
}
@@ -623,7 +623,7 @@ class SimpleThread : public ThreadState, public ThreadContext
vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val;
}
const VecElem &
const TheISA::VecElem &
readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override
{
return vecRegs[reg].as<TheISA::VecElem>()[elemIndex];
@@ -631,25 +631,26 @@ class SimpleThread : public ThreadState, public ThreadContext
void
setVecElemFlat(RegIndex reg, const ElemIndex &elemIndex,
const VecElem &val) override
const TheISA::VecElem &val) override
{
vecRegs[reg].as<TheISA::VecElem>()[elemIndex] = val;
}
const VecPredRegContainer &
const TheISA::VecPredRegContainer &
readVecPredRegFlat(RegIndex reg) const override
{
return vecPredRegs[reg];
}
VecPredRegContainer &
TheISA::VecPredRegContainer &
getWritableVecPredRegFlat(RegIndex reg) override
{
return vecPredRegs[reg];
}
void
setVecPredRegFlat(RegIndex reg, const VecPredRegContainer &val) override
setVecPredRegFlat(RegIndex reg,
const TheISA::VecPredRegContainer &val) override
{
vecPredRegs[reg] = val;
}

8
src/cpu/static_inst.hh
View File

@@ -85,9 +85,6 @@ class InstRecord;
class StaticInst : public RefCounted, public StaticInstFlags
{
public:
/// Binary extended machine instruction type.
typedef TheISA::ExtMachInst ExtMachInst;
using RegIdArrayPtr = RegId (StaticInst:: *)[];
private:
@@ -259,7 +256,7 @@ class StaticInst : public RefCounted, public StaticInstFlags
static StaticInstPtr nopStaticInstPtr;
/// The binary machine instruction.
const ExtMachInst machInst;
const TheISA::ExtMachInst machInst;
protected:
@@ -301,7 +298,8 @@ class StaticInst : public RefCounted, public StaticInstFlags
/// default, since the decoder generally only overrides
/// the fields that are meaningful for the particular
/// instruction.
StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
StaticInst(const char *_mnemonic, TheISA::ExtMachInst _machInst,
OpClass __opClass)
: _opClass(__opClass),
_numSrcRegs(0), _numDestRegs(0), _numFPDestRegs(0),
_numIntDestRegs(0), _numCCDestRegs(0), _numVecDestRegs(0),

45
src/cpu/thread_context.hh
View File

@@ -88,9 +88,6 @@ class System;
class ThreadContext : public PCEventScope
{
protected:
using VecRegContainer = TheISA::VecRegContainer;
using VecElem = TheISA::VecElem;
using VecPredRegContainer = TheISA::VecPredRegContainer;
bool useForClone = false;
public:
@@ -207,8 +204,9 @@ class ThreadContext : public PCEventScope
virtual RegVal readFloatReg(RegIndex reg_idx) const = 0;
virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
virtual const TheISA::VecRegContainer&
readVecReg(const RegId& reg) const = 0;
virtual TheISA::VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
/** Vector Register Lane Interfaces. */
/** @{ */
@@ -239,11 +237,12 @@ class ThreadContext : public PCEventScope
const LaneData<LaneSize::EightByte>& val) = 0;
/** @} */
virtual const VecElem& readVecElem(const RegId& reg) const = 0;
virtual const TheISA::VecElem& readVecElem(const RegId& reg) const = 0;
virtual const VecPredRegContainer& readVecPredReg(const RegId& reg)
const = 0;
virtual VecPredRegContainer& getWritableVecPredReg(const RegId& reg) = 0;
virtual const TheISA::VecPredRegContainer& readVecPredReg(
const RegId& reg) const = 0;
virtual TheISA::VecPredRegContainer& getWritableVecPredReg(
const RegId& reg) = 0;
virtual RegVal readCCReg(RegIndex reg_idx) const = 0;
@@ -251,12 +250,13 @@ class ThreadContext : public PCEventScope
virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0;
virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
virtual void setVecReg(const RegId& reg,
const TheISA::VecRegContainer& val) = 0;
virtual void setVecElem(const RegId& reg, const VecElem& val) = 0;
virtual void setVecElem(const RegId& reg, const TheISA::VecElem& val) = 0;
virtual void setVecPredReg(const RegId& reg,
const VecPredRegContainer& val) = 0;
const TheISA::VecPredRegContainer& val) = 0;
virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0;
@@ -325,20 +325,23 @@ class ThreadContext : public PCEventScope
virtual RegVal readFloatRegFlat(RegIndex idx) const = 0;
virtual void setFloatRegFlat(RegIndex idx, RegVal val) = 0;
virtual const VecRegContainer& readVecRegFlat(RegIndex idx) const = 0;
virtual VecRegContainer& getWritableVecRegFlat(RegIndex idx) = 0;
virtual void setVecRegFlat(RegIndex idx, const VecRegContainer& val) = 0;
virtual const TheISA::VecRegContainer&
readVecRegFlat(RegIndex idx) const = 0;
virtual TheISA::VecRegContainer& getWritableVecRegFlat(RegIndex idx) = 0;
virtual void setVecRegFlat(RegIndex idx,
const TheISA::VecRegContainer& val) = 0;
virtual const VecElem& readVecElemFlat(RegIndex idx,
const ElemIndex& elemIdx) const = 0;
virtual const TheISA::VecElem& readVecElemFlat(RegIndex idx,
const ElemIndex& elemIdx) const = 0;
virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
const VecElem& val) = 0;
const TheISA::VecElem& val) = 0;
virtual const VecPredRegContainer &
virtual const TheISA::VecPredRegContainer &
readVecPredRegFlat(RegIndex idx) const = 0;
virtual VecPredRegContainer& getWritableVecPredRegFlat(RegIndex idx) = 0;
virtual TheISA::VecPredRegContainer& getWritableVecPredRegFlat(
RegIndex idx) = 0;
virtual void setVecPredRegFlat(RegIndex idx,
const VecPredRegContainer& val) = 0;
const TheISA::VecPredRegContainer& val) = 0;
virtual RegVal readCCRegFlat(RegIndex idx) const = 0;
virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0;