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mips: Stop using architecture specific register types.

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Change-Id: I764f6eea214ba4e03cc0fe19a21abcb0ebd04408
Reviewed-on: https://gem5-review.googlesource.com/c/14462
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
This commit is contained in:
Gabe Black
2018-11-19 18:37:16 -08:00
parent c8a744f919
commit cdfb486458
8 changed files with 45 additions and 54 deletions
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4
src/arch/mips/interrupts.cc
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@@ -145,8 +145,8 @@ Interrupts::getInterrupt(ThreadContext * tc)
bool
Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const
{
MiscReg compare = tc->readMiscRegNoEffect(MISCREG_COMPARE);
MiscReg count = tc->readMiscRegNoEffect(MISCREG_COUNT);
RegVal compare = tc->readMiscRegNoEffect(MISCREG_COMPARE);
RegVal count = tc->readMiscRegNoEffect(MISCREG_COUNT);
if (compare == count && count != 0)
return true;
return false;

48
src/arch/mips/isa.cc
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@@ -185,7 +185,7 @@ ISA::configCP()
setMiscRegNoEffect(MISCREG_PRID, procId);
// Now, create Write Mask for ProcID register
MiscReg procIDMask = 0; // Read-Only register
RegVal procIDMask = 0; // Read-Only register
replaceBits(procIDMask, 0, 32, 0);
setRegMask(MISCREG_PRID, procIDMask);
@@ -199,7 +199,7 @@ ISA::configCP()
cfg.m = 1;
setMiscRegNoEffect(MISCREG_CONFIG, cfg);
// Now, create Write Mask for Config register
MiscReg cfg_Mask = 0x7FFF0007;
RegVal cfg_Mask = 0x7FFF0007;
replaceBits(cfg_Mask, 0, 32, 0);
setRegMask(MISCREG_CONFIG, cfg_Mask);
@@ -221,7 +221,7 @@ ISA::configCP()
cfg1.m = cp.CP0_Config1_M;
setMiscRegNoEffect(MISCREG_CONFIG1, cfg1);
// Now, create Write Mask for Config register
MiscReg cfg1_Mask = 0; // Read Only Register
RegVal cfg1_Mask = 0; // Read Only Register
replaceBits(cfg1_Mask, 0, 32, 0);
setRegMask(MISCREG_CONFIG1, cfg1_Mask);
@@ -238,7 +238,7 @@ ISA::configCP()
cfg2.m = cp.CP0_Config2_M;
setMiscRegNoEffect(MISCREG_CONFIG2, cfg2);
// Now, create Write Mask for Config register
MiscReg cfg2_Mask = 0x7000F000; // Read Only Register
RegVal cfg2_Mask = 0x7000F000; // Read Only Register
replaceBits(cfg2_Mask, 0, 32, 0);
setRegMask(MISCREG_CONFIG2, cfg2_Mask);
@@ -254,7 +254,7 @@ ISA::configCP()
cfg3.tl = cp.CP0_Config3_TL;
setMiscRegNoEffect(MISCREG_CONFIG3, cfg3);
// Now, create Write Mask for Config register
MiscReg cfg3_Mask = 0; // Read Only Register
RegVal cfg3_Mask = 0; // Read Only Register
replaceBits(cfg3_Mask, 0, 32, 0);
setRegMask(MISCREG_CONFIG3, cfg3_Mask);
@@ -264,7 +264,7 @@ ISA::configCP()
replaceBits(eBase, 31, 31, 1);
setMiscRegNoEffect(MISCREG_EBASE, eBase);
// Now, create Write Mask for Config register
MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the
RegVal EB_Mask = 0x3FFFF000;// Except Exception Base, the
// entire register is read only
replaceBits(EB_Mask, 0, 32, 0);
setRegMask(MISCREG_EBASE, EB_Mask);
@@ -274,7 +274,7 @@ ISA::configCP()
scsCtl.hss = cp.CP0_SrsCtl_HSS;
setMiscRegNoEffect(MISCREG_SRSCTL, scsCtl);
// Now, create Write Mask for the SRS Ctl register
MiscReg SC_Mask = 0x0000F3C0;
RegVal SC_Mask = 0x0000F3C0;
replaceBits(SC_Mask, 0, 32, 0);
setRegMask(MISCREG_SRSCTL, SC_Mask);
@@ -284,7 +284,7 @@ ISA::configCP()
intCtl.ippci = cp.CP0_IntCtl_IPPCI;
setMiscRegNoEffect(MISCREG_INTCTL, intCtl);
// Now, create Write Mask for the IntCtl register
MiscReg IC_Mask = 0x000003E0;
RegVal IC_Mask = 0x000003E0;
replaceBits(IC_Mask, 0, 32, 0);
setRegMask(MISCREG_INTCTL, IC_Mask);
@@ -293,7 +293,7 @@ ISA::configCP()
watchHi.m = cp.CP0_WatchHi_M;
setMiscRegNoEffect(MISCREG_WATCHHI0, watchHi);
// Now, create Write Mask for the IntCtl register
MiscReg wh_Mask = 0x7FFF0FFF;
RegVal wh_Mask = 0x7FFF0FFF;
replaceBits(wh_Mask, 0, 32, 0);
setRegMask(MISCREG_WATCHHI0, wh_Mask);
@@ -303,14 +303,14 @@ ISA::configCP()
perfCntCtl.w = cp.CP0_PerfCtr_W;
setMiscRegNoEffect(MISCREG_PERFCNT0, perfCntCtl);
// Now, create Write Mask for the IntCtl register
MiscReg pc_Mask = 0x00007FF;
RegVal pc_Mask = 0x00007FF;
replaceBits(pc_Mask, 0, 32, 0);
setRegMask(MISCREG_PERFCNT0, pc_Mask);
// Random
setMiscRegNoEffect(MISCREG_CP0_RANDOM, 63);
// Now, create Write Mask for the IntCtl register
MiscReg random_Mask = 0;
RegVal random_Mask = 0;
replaceBits(random_Mask, 0, 32, 0);
setRegMask(MISCREG_CP0_RANDOM, random_Mask);
@@ -319,7 +319,7 @@ ISA::configCP()
pageGrain.esp = cp.CP0_Config3_SP;
setMiscRegNoEffect(MISCREG_PAGEGRAIN, pageGrain);
// Now, create Write Mask for the IntCtl register
MiscReg pg_Mask = 0x10000000;
RegVal pg_Mask = 0x10000000;
replaceBits(pg_Mask, 0, 32, 0);
setRegMask(MISCREG_PAGEGRAIN, pg_Mask);
@@ -338,7 +338,7 @@ ISA::configCP()
setMiscRegNoEffect(MISCREG_STATUS, status);
// Now, create Write Mask for the Status register
MiscReg stat_Mask = 0xFF78FF17;
RegVal stat_Mask = 0xFF78FF17;
replaceBits(stat_Mask, 0, 32, 0);
setRegMask(MISCREG_STATUS, stat_Mask);
@@ -380,7 +380,7 @@ ISA::configCP()
}
MiscReg mask = 0x7FFFFFFF;
RegVal mask = 0x7FFFFFFF;
// Now, create Write Mask for the Index register
replaceBits(mask, 0, 32, 0);
@@ -417,7 +417,7 @@ ISA::getVPENum(ThreadID tid) const
return tcBind.curVPE;
}
MiscReg
RegVal
ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
{
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
@@ -431,7 +431,7 @@ ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
//@TODO: MIPS MT's register view automatically connects
// Status to TCStatus depending on current thread
//template <class TC>
MiscReg
RegVal
ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
{
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
@@ -445,7 +445,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
}
void
ISA::setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid)
ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
{
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
@@ -458,7 +458,7 @@ ISA::setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid)
}
void
ISA::setRegMask(int misc_reg, MiscReg val, ThreadID tid)
ISA::setRegMask(int misc_reg, RegVal val, ThreadID tid)
{
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
@@ -473,7 +473,7 @@ ISA::setRegMask(int misc_reg, MiscReg val, ThreadID tid)
// be overwritten. Make sure to handle those particular registers
// with care!
void
ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc, ThreadID tid)
ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid)
{
int reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
@@ -483,7 +483,7 @@ ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc, ThreadID tid)
"Select:%u (%s) to %#x, with effect.\n",
tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val);
RegVal cp0_val = filterCP0Write(misc_reg, reg_sel, val);
miscRegFile[misc_reg][reg_sel] = cp0_val;
@@ -495,14 +495,14 @@ ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc, ThreadID tid)
* since it has already been done in the calling method
* (setRegWithEffect)
*/
MiscReg
ISA::filterCP0Write(int misc_reg, int reg_sel, MiscReg val)
RegVal
ISA::filterCP0Write(int misc_reg, int reg_sel, RegVal val)
{
MiscReg retVal = val;
RegVal retVal = val;
// Mask off read-only regions
retVal &= miscRegFile_WriteMask[misc_reg][reg_sel];
MiscReg curVal = miscRegFile[misc_reg][reg_sel];
RegVal curVal = miscRegFile[misc_reg][reg_sel];
// Mask off current alue with inverse mask (clear writeable bits)
curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]);
retVal |= curVal; // Combine the two

17
src/arch/mips/isa.hh
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@@ -68,8 +68,8 @@ namespace MipsISA
perVirtProcessor
};
std::vector<std::vector<MiscReg> > miscRegFile;
std::vector<std::vector<MiscReg> > miscRegFile_WriteMask;
std::vector<std::vector<RegVal> > miscRegFile;
std::vector<std::vector<RegVal> > miscRegFile_WriteMask;
std::vector<BankType> bankType;
public:
@@ -88,18 +88,17 @@ namespace MipsISA
//@TODO: MIPS MT's register view automatically connects
// Status to TCStatus depending on current thread
void updateCP0ReadView(int misc_reg, ThreadID tid) { }
MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
//template <class TC>
MiscReg readMiscReg(int misc_reg,
ThreadContext *tc, ThreadID tid = 0);
RegVal readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
MiscReg filterCP0Write(int misc_reg, int reg_sel, MiscReg val);
void setRegMask(int misc_reg, MiscReg val, ThreadID tid = 0);
void setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid=0);
RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val);
void setRegMask(int misc_reg, RegVal val, ThreadID tid = 0);
void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0);
//template <class TC>
void setMiscReg(int misc_reg, MiscReg val,
void setMiscReg(int misc_reg, RegVal val,
ThreadContext *tc, ThreadID tid=0);
//////////////////////////////////////////////////////////

10
src/arch/mips/isa/formats/control.isa
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@@ -192,9 +192,9 @@ output exec {{
if (!FullSystem)
return true;
MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
RegVal Stat = xc->readMiscReg(MISCREG_STATUS);
if (cop_num == 0) {
MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
RegVal Dbg = xc->readMiscReg(MISCREG_DEBUG);
// In Stat, EXL, ERL or CU0 set, CP0 accessible
// In Dbg, DM bit set, CP0 accessible
// In Stat, KSU = 0, kernel mode is base mode
@@ -212,8 +212,8 @@ output exec {{
isCoprocessor0Enabled(ExecContext *xc)
{
if (FullSystem) {
MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
RegVal Stat = xc->readMiscReg(MISCREG_STATUS);
RegVal Dbg = xc->readMiscReg(MISCREG_DEBUG);
// In Stat, EXL, ERL or CU0 set, CP0 accessible
// In Dbg, DM bit set, CP0 accessible
// In Stat KSU = 0, kernel mode is base mode
@@ -227,7 +227,7 @@ output exec {{
bool
isMMUTLB(ExecContext *xc)
{
MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
RegVal Config = xc->readMiscReg(MISCREG_CONFIG);
return FullSystem && (Config & 0x380) == 0x80;
}
}};

4
src/arch/mips/process.cc
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@@ -201,7 +201,7 @@ MipsProcess::argsInit(int pageSize)
}
MipsISA::IntReg
RegVal
MipsProcess::getSyscallArg(ThreadContext *tc, int &i)
{
assert(i < 6);
@@ -209,7 +209,7 @@ MipsProcess::getSyscallArg(ThreadContext *tc, int &i)
}
void
MipsProcess::setSyscallArg(ThreadContext *tc, int i, MipsISA::IntReg val)
MipsProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val)
{
assert(i < 6);
tc->setIntReg(FirstArgumentReg + i, val);

4
src/arch/mips/process.hh
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@@ -51,10 +51,10 @@ class MipsProcess : public Process
void argsInit(int pageSize);
public:
MipsISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
RegVal getSyscallArg(ThreadContext *tc, int &i);
/// Explicitly import the otherwise hidden getSyscallArg
using Process::getSyscallArg;
void setSyscallArg(ThreadContext *tc, int i, MipsISA::IntReg val);
void setSyscallArg(ThreadContext *tc, int i, RegVal val);
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
};

8
src/arch/mips/registers.hh
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@@ -283,14 +283,6 @@ const int NumMiscRegs = MISCREG_NUMREGS;
const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
typedef RegVal IntReg;
// floating point register file entry type
typedef RegVal FloatReg;
// cop-0/cop-1 system control register
typedef RegVal MiscReg;
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;

4
src/arch/mips/utility.hh
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@@ -74,8 +74,8 @@ bool isSnan(void *val_ptr, int size);
static inline bool
inUserMode(ThreadContext *tc)
{
MiscReg Stat = tc->readMiscReg(MISCREG_STATUS);
MiscReg Dbg = tc->readMiscReg(MISCREG_DEBUG);
RegVal Stat = tc->readMiscReg(MISCREG_STATUS);
RegVal Dbg = tc->readMiscReg(MISCREG_DEBUG);
if ((Stat & 0x10000006) == 0 && // EXL, ERL or CU0 set, CP0 accessible
(Dbg & 0x40000000) == 0 && // DM bit set, CP0 accessible