derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-arm: Writes to DCCMVAC shouldn't flush pipeline

Browse Source 
Writes to DCCMVAC (Data Cache line Clean by VA to PoC) system register
shouldn't flush the pipeline as a result of the operation. This addition
was wrongly introduced for supporting self-modifying code. Software
barriers should be used instead.

Change-Id: Idf0c27d2e49ca01be19888ae5523b8f8eaefa7b3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5362
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2017-10-23 10:49:38 +01:00
committed by Andreas Sandberg
parent 053bb85b32
commit ccdbc394e2
1 changed files with 0 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/arch/arm/insts/pseudo.cc
View File

@@ -190,9 +190,6 @@ McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
flags[IsNonSpeculative] = true;
iss = _iss;
miscReg = _miscReg;
if (miscReg == MISCREG_DCCMVAC)
flags[IsSquashAfter] = true;
}
Fault