Ruby: Reorganize mapping of components
In RubySlicc_ComponentMapping.hh, certain '#define's have been used for mapping MachineType to GenericMachineType. These '#define's are being eliminated and the code will now be generated by SLICC instead. Also are being eliminated some of the unused functions from RubySlicc_ComponentMapping.sm.
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@@ -30,34 +30,12 @@
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// Mapping functions
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int machineCount(MachineType machType);
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// NodeID map_address_to_node(Address addr);
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MachineID mapAddressToRange(Address addr, MachineType type, int low, int high);
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NetDest broadcast(MachineType type);
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MachineID map_Address_to_DMA(Address addr);
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MachineID map_Address_to_Directory(Address addr);
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NodeID map_Address_to_DirectoryNode(Address addr);
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MachineID getL1MachineID(NodeID L1RubyNode);
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NodeID getChipID(MachineID L2machID);
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MachineID getCollectorDest(MachineID L1machID);
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MachineID getCollectorL1Cache(MachineID colID);
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NetDest getMultiStaticL2BankNetDest(Address addr, Set sharers);
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bool isL1OnChip(MachineID L1machID, NodeID L2NodeID);
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bool isL2OnChip(MachineID L2machID, NodeID L2NodeID);
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int getNumBanksInBankSet();
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NodeID machineIDToNodeID(MachineID machID);
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NodeID machineIDToVersion(MachineID machID);
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MachineType machineIDToMachineType(MachineID machID);
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NodeID L1CacheMachIDToProcessorNum(MachineID machID);
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NodeID L2CacheMachIDToChipID(MachineID machID);
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Set getOtherLocalL1IDs(MachineID L1);
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Set getLocalL1IDs(MachineID L1);
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Set getExternalL1IDs(MachineID L1);
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NetDest getAllPertinentL2Banks(Address addr);
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bool isLocalProcessor(MachineID thisId, MachineID tarId);
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GenericMachineType ConvertMachToGenericMach(MachineType machType);
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@@ -29,7 +29,6 @@
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#ifndef __MEM_RUBY_SLICC_INTERFACE_RUBYSLICC_COMPONENTMAPPINGS_HH__
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#define __MEM_RUBY_SLICC_INTERFACE_RUBYSLICC_COMPONENTMAPPINGS_HH__
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#include "mem/protocol/GenericMachineType.hh"
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#include "mem/protocol/MachineType.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/common/Global.hh"
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@@ -38,30 +37,6 @@
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#include "mem/ruby/system/MachineID.hh"
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#include "mem/ruby/system/NodeID.hh"
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#ifdef MACHINETYPE_L1Cache
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#define MACHINETYPE_L1CACHE_ENUM MachineType_L1Cache
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#else
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#define MACHINETYPE_L1CACHE_ENUM MachineType_NUM
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#endif
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#ifdef MACHINETYPE_L2Cache
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#define MACHINETYPE_L2CACHE_ENUM MachineType_L2Cache
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#else
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#define MACHINETYPE_L2CACHE_ENUM MachineType_NUM
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#endif
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#ifdef MACHINETYPE_L3Cache
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#define MACHINETYPE_L3CACHE_ENUM MachineType_L3Cache
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#else
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#define MACHINETYPE_L3CACHE_ENUM MachineType_NUM
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#endif
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#ifdef MACHINETYPE_DMA
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#define MACHINETYPE_DMA_ENUM MachineType_DMA
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#else
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#define MACHINETYPE_DMA_ENUM MachineType_NUM
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#endif
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// used to determine the home directory
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// returns a value between 0 and total_directories_within_the_system
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inline NodeID
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@@ -80,13 +55,6 @@ map_Address_to_Directory(const Address &addr)
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return mach;
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}
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inline MachineID
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map_Address_to_DMA(const Address & addr)
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{
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MachineID dma = {MACHINETYPE_DMA_ENUM, 0};
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return dma;
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}
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inline NetDest
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broadcast(MachineType type)
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{
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@@ -121,41 +89,6 @@ machineIDToMachineType(MachineID machID)
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return machID.type;
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}
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inline NodeID
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L1CacheMachIDToProcessorNum(MachineID machID)
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{
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assert(machID.type == MACHINETYPE_L1CACHE_ENUM);
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return machID.num;
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}
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inline MachineID
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getL1MachineID(NodeID L1RubyNode)
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{
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MachineID mach = {MACHINETYPE_L1CACHE_ENUM, L1RubyNode};
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return mach;
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}
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inline GenericMachineType
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ConvertMachToGenericMach(MachineType machType)
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{
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if (machType == MACHINETYPE_L1CACHE_ENUM)
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return GenericMachineType_L1Cache;
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if (machType == MACHINETYPE_L2CACHE_ENUM)
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return GenericMachineType_L2Cache;
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if (machType == MACHINETYPE_L3CACHE_ENUM)
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return GenericMachineType_L3Cache;
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if (machType == MachineType_Directory)
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return GenericMachineType_Directory;
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if (machType == MACHINETYPE_DMA_ENUM)
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return GenericMachineType_DMA;
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panic("cannot convert to a GenericMachineType");
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}
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inline int
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machineCount(MachineType machType)
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{
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@@ -444,6 +444,13 @@ ${{self.c_ident}}::print(ostream& out) const
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if self.isStateDecl:
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code('#include "mem/protocol/AccessPermission.hh"')
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if self.isMachineType:
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code('#include "base/misc.hh"')
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code('#include "mem/protocol/GenericMachineType.hh"')
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code('#include "mem/ruby/common/Address.hh"')
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code('#include "mem/ruby/system/NodeID.hh"')
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code('struct MachineID;')
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code('''
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// Class definition
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@@ -488,7 +495,29 @@ int ${{self.c_ident}}_base_count(const ${{self.c_ident}}& obj);
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''')
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for enum in self.enums.itervalues():
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code('#define MACHINETYPE_${{enum.ident}} 1')
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if enum.ident == "DMA":
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code('''
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MachineID map_Address_to_DMA(const Address &addr);
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''')
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code('''
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MachineID get${{enum.ident}}MachineID(NodeID RubyNode);
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''')
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code('''
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inline GenericMachineType
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ConvertMachToGenericMach(MachineType machType)
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{
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''')
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for enum in self.enums.itervalues():
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code('''
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if (machType == MachineType_${{enum.ident}})
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return GenericMachineType_${{enum.ident}};
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''')
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code('''
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panic("cannot convert to a GenericMachineType");
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}
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''')
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if self.isStateDecl:
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code('''
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@@ -550,6 +579,7 @@ AccessPermission ${{self.c_ident}}_to_permission(const ${{self.c_ident}}& obj)
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if self.isMachineType:
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for enum in self.enums.itervalues():
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code('#include "mem/protocol/${{enum.ident}}_Controller.hh"')
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code('#include "mem/ruby/system/MachineID.hh"')
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code('''
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// Code for output operator
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@@ -721,6 +751,27 @@ ${{self.c_ident}}_base_count(const ${{self.c_ident}}& obj)
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panic("Invalid range for type ${{self.c_ident}}");
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}
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}
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''')
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for enum in self.enums.itervalues():
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if enum.ident == "DMA":
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code('''
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MachineID
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map_Address_to_DMA(const Address &addr)
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{
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MachineID dma = {MachineType_DMA, 0};
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return dma;
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}
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''')
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code('''
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MachineID
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get${{enum.ident}}MachineID(NodeID RubyNode)
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{
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MachineID mach = {MachineType_${{enum.ident}}, RubyNode};
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return mach;
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}
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''')
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# Write the file
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