Slowly on our way to booting with Tsunami
--HG-- extra : convert_revision : ec8e7e2dc929ad84c5e320fbfb02070e94cd1ad1
This commit is contained in:
Ali Saidi
99
dev/tsunami.cc
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99
dev/tsunami.cc
Normal file
@@ -0,0 +1,99 @@
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/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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||||
*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "cpu/intr_control.hh"
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#include "dev/console.hh"
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#include "dev/etherdev.hh"
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#include "dev/scsi_ctrl.hh"
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#include "dev/tlaser_clock.hh"
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#include "dev/tsunami_cchip.hh"
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#include "dev/tsunami.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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Tsunami::Tsunami(const string &name, ScsiController *s, EtherDev *e,
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TlaserClock *c, TsunamiCChip *cc, SimConsole *con,
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IntrControl *ic, int intr_freq)
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: SimObject(name), intctrl(ic), cons(con), scsi(s), ethernet(e),
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clock(c), cchip(cc), interrupt_frequency(intr_freq)
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{
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for (int i = 0; i < Tsunami::Max_CPUs; i++)
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intr_sum_type[i] = 0;
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}
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void
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Tsunami::serialize(std::ostream &os)
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{
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SERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
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}
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void
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Tsunami::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
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SimObjectParam<ScsiController *> scsi;
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SimObjectParam<EtherDev *> ethernet;
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SimObjectParam<TlaserClock *> clock;
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SimObjectParam<TsunamiCChip *> cchip;
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SimObjectParam<SimConsole *> cons;
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SimObjectParam<IntrControl *> intrctrl;
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Param<int> interrupt_frequency;
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END_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
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BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami)
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INIT_PARAM(scsi, "scsi controller"),
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INIT_PARAM(ethernet, "ethernet controller"),
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INIT_PARAM(clock, "turbolaser clock"),
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INIT_PARAM(cchip, "cchip"),
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INIT_PARAM(cons, "system console"),
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INIT_PARAM(intrctrl, "interrupt controller"),
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INIT_PARAM_DFLT(interrupt_frequency, "frequency of interrupts", 1200)
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END_INIT_SIM_OBJECT_PARAMS(Tsunami)
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CREATE_SIM_OBJECT(Tsunami)
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{
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return new Tsunami(getInstanceName(), scsi, ethernet, clock,
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cchip, cons, intrctrl, interrupt_frequency);
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}
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REGISTER_SIM_OBJECT("Tsunami", Tsunami)
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73
dev/tsunami.hh
Normal file
73
dev/tsunami.hh
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@@ -0,0 +1,73 @@
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/*
|
||||
* Copyright (c) 2003 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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#ifndef __TSUNAMI_HH__
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#define __TSUNAMI_HH__
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#include "sim/sim_object.hh"
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class IntrControl;
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class ConsoleListener;
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class SimConsole;
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class ScsiController;
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class TlaserClock;
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class EtherDev;
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class TsunamiCChip;
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class Tsunami : public SimObject
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{
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public:
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static const int Max_CPUs = 4;
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IntrControl *intctrl;
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// ConsoleListener *listener;
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SimConsole *cons;
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ScsiController *scsi;
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EtherDev *ethernet;
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TlaserClock *clock;
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TsunamiCChip *cchip;
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int intr_sum_type[Tsunami::Max_CPUs];
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int ipi_pending[Tsunami::Max_CPUs];
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int interrupt_frequency;
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public:
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Tsunami(const std::string &name, ScsiController *scsi,
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EtherDev *ethernet, TlaserClock *clock, TsunamiCChip *tc,
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SimConsole *, IntrControl *intctrl,
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int intrFreq);
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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};
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#endif // __TSUNAMI_HH__
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236
dev/tsunami_cchip.cc
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236
dev/tsunami_cchip.cc
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@@ -0,0 +1,236 @@
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/* $Id$ */
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/* @file
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* Tsunami CChip (processor, memory, or IO)
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "cpu/exec_context.hh"
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#include "dev/console.hh"
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#include "dev/etherdev.hh"
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#include "dev/scsi_ctrl.hh"
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#include "dev/tlaser_clock.hh"
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#include "dev/tsunami_cchip.hh"
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#include "dev/tsunamireg.h"
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#include "dev/tsunami.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t,
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Addr addr, Addr mask, MemoryController *mmu)
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: MmapDevice(name, addr, mask, mmu), tsunami(t)
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||||
{
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for(int i=0; i < Tsunami::Max_CPUs; i++) {
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dim[i] = 0;
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dir[i] = 0;
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}
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drir = 0;
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}
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Fault
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TsunamiCChip::read(MemReqPtr req, uint8_t *data)
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{
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DPRINTF(Tsunami, "cchip read va=%#x size=%d\n",
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req->vaddr, req->size);
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Addr daddr = (req->paddr & addr_mask) >> 6;
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// ExecContext *xc = req->xc;
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// int cpuid = xc->cpu_id;
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switch (req->size) {
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case sizeof(uint64_t):
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switch(daddr) {
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case TSDEV_CC_CSR:
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*(uint64_t*)data = 0x0;
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return No_Fault;
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case TSDEV_CC_MTR:
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panic("TSDEV_CC_MTR not implemeted\n");
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return No_Fault;
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case TSDEV_CC_MISC:
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panic("TSDEV_CC_MISC not implemented\n");
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return No_Fault;
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case TSDEV_CC_AAR0:
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case TSDEV_CC_AAR1:
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case TSDEV_CC_AAR2:
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case TSDEV_CC_AAR3:
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panic("TSDEV_CC_AARx not implemeted\n");
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return No_Fault;
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case TSDEV_CC_DIM0:
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*(uint64_t*)data = dim[0];
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return No_Fault;
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case TSDEV_CC_DIM1:
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*(uint64_t*)data = dim[1];
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return No_Fault;
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case TSDEV_CC_DIM2:
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*(uint64_t*)data = dim[2];
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return No_Fault;
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case TSDEV_CC_DIM3:
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*(uint64_t*)data = dim[3];
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return No_Fault;
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case TSDEV_CC_DIR0:
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*(uint64_t*)data = dir[0];
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return No_Fault;
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case TSDEV_CC_DIR1:
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*(uint64_t*)data = dir[1];
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return No_Fault;
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case TSDEV_CC_DIR2:
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*(uint64_t*)data = dir[2];
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return No_Fault;
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||||
case TSDEV_CC_DIR3:
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*(uint64_t*)data = dir[3];
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||||
return No_Fault;
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case TSDEV_CC_DRIR:
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*(uint64_t*)data = drir;
|
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return No_Fault;
|
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case TSDEV_CC_PRBEN:
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panic("TSDEV_CC_PRBEN not implemented\n");
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return No_Fault;
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case TSDEV_CC_IIC0:
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case TSDEV_CC_IIC1:
|
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case TSDEV_CC_IIC2:
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case TSDEV_CC_IIC3:
|
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panic("TSDEV_CC_IICx not implemented\n");
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return No_Fault;
|
||||
case TSDEV_CC_MPR0:
|
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case TSDEV_CC_MPR1:
|
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case TSDEV_CC_MPR2:
|
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case TSDEV_CC_MPR3:
|
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panic("TSDEV_CC_MPRx not implemented\n");
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return No_Fault;
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} // uint64_t
|
||||
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break;
|
||||
case sizeof(uint32_t):
|
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case sizeof(uint16_t):
|
||||
case sizeof(uint8_t):
|
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default:
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panic("invalid access size(?) for tsunami register!");
|
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}
|
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DPRINTFN("Tsunami CChip ERROR: read daddr=%#x size=%d\n", daddr, req->size);
|
||||
|
||||
return No_Fault;
|
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}
|
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|
||||
Fault
|
||||
TsunamiCChip::write(MemReqPtr req, const uint8_t *data)
|
||||
{
|
||||
DPRINTF(Tsunami, "Tsunami CChip write - va=%#x size=%d \n",
|
||||
req->vaddr, req->size);
|
||||
|
||||
Addr daddr = (req->paddr & addr_mask) >> 6;
|
||||
|
||||
switch (req->size) {
|
||||
|
||||
case sizeof(uint64_t):
|
||||
switch(daddr) {
|
||||
case TSDEV_CC_CSR:
|
||||
panic("TSDEV_CC_CSR write\n");
|
||||
return No_Fault;
|
||||
case TSDEV_CC_MTR:
|
||||
panic("TSDEV_CC_MTR write not implemented\n");
|
||||
return No_Fault;
|
||||
case TSDEV_CC_MISC:
|
||||
panic("TSDEV_CC_MISC write not implemented\n");
|
||||
return No_Fault;
|
||||
case TSDEV_CC_AAR0:
|
||||
case TSDEV_CC_AAR1:
|
||||
case TSDEV_CC_AAR2:
|
||||
case TSDEV_CC_AAR3:
|
||||
panic("TSDEV_CC_AARx write not implemeted\n");
|
||||
return No_Fault;
|
||||
case TSDEV_CC_DIM0:
|
||||
dim[0] = *(uint64_t*)data;
|
||||
return No_Fault;
|
||||
case TSDEV_CC_DIM1:
|
||||
dim[1] = *(uint64_t*)data;
|
||||
return No_Fault;
|
||||
case TSDEV_CC_DIM2:
|
||||
dim[2] = *(uint64_t*)data;
|
||||
return No_Fault;
|
||||
case TSDEV_CC_DIM3:
|
||||
dim[3] = *(uint64_t*)data;
|
||||
return No_Fault;
|
||||
case TSDEV_CC_DIR0:
|
||||
case TSDEV_CC_DIR1:
|
||||
case TSDEV_CC_DIR2:
|
||||
case TSDEV_CC_DIR3:
|
||||
panic("TSDEV_CC_DIR write not implemented\n");
|
||||
return No_Fault;
|
||||
case TSDEV_CC_DRIR:
|
||||
panic("TSDEV_CC_DRIR write not implemented\n");
|
||||
return No_Fault;
|
||||
case TSDEV_CC_PRBEN:
|
||||
panic("TSDEV_CC_PRBEN write not implemented\n");
|
||||
return No_Fault;
|
||||
case TSDEV_CC_IIC0:
|
||||
case TSDEV_CC_IIC1:
|
||||
case TSDEV_CC_IIC2:
|
||||
case TSDEV_CC_IIC3:
|
||||
panic("TSDEV_CC_IICx write not implemented\n");
|
||||
return No_Fault;
|
||||
case TSDEV_CC_MPR0:
|
||||
case TSDEV_CC_MPR1:
|
||||
case TSDEV_CC_MPR2:
|
||||
case TSDEV_CC_MPR3:
|
||||
panic("TSDEV_CC_MPRx write not implemented\n");
|
||||
return No_Fault;
|
||||
}
|
||||
|
||||
break;
|
||||
case sizeof(uint32_t):
|
||||
case sizeof(uint16_t):
|
||||
case sizeof(uint8_t):
|
||||
default:
|
||||
panic("invalid access size(?) for tsunami register!");
|
||||
}
|
||||
|
||||
DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
|
||||
|
||||
return No_Fault;
|
||||
}
|
||||
|
||||
void
|
||||
TsunamiCChip::serialize(std::ostream &os)
|
||||
{
|
||||
// code should be written
|
||||
}
|
||||
|
||||
void
|
||||
TsunamiCChip::unserialize(Checkpoint *cp, const std::string §ion)
|
||||
{
|
||||
//code should be written
|
||||
}
|
||||
|
||||
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
|
||||
|
||||
SimObjectParam<Tsunami *> tsunami;
|
||||
SimObjectParam<MemoryController *> mmu;
|
||||
Param<Addr> addr;
|
||||
Param<Addr> mask;
|
||||
|
||||
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
|
||||
|
||||
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
|
||||
|
||||
INIT_PARAM(tsunami, "Tsunami"),
|
||||
INIT_PARAM(mmu, "Memory Controller"),
|
||||
INIT_PARAM(addr, "Device Address"),
|
||||
INIT_PARAM(mask, "Address Mask")
|
||||
|
||||
END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
|
||||
|
||||
CREATE_SIM_OBJECT(TsunamiCChip)
|
||||
{
|
||||
return new TsunamiCChip(getInstanceName(), tsunami, addr, mask, mmu);
|
||||
}
|
||||
|
||||
REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
|
||||
63
dev/tsunami_cchip.hh
Normal file
63
dev/tsunami_cchip.hh
Normal file
@@ -0,0 +1,63 @@
|
||||
/*
|
||||
* Copyright (c) 2003 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/* @file
|
||||
* Turbolaser system bus node (processor, memory, or IO)
|
||||
*/
|
||||
|
||||
#ifndef __TSUNAMI_CCHIP_HH__
|
||||
#define __TSUNAMI_CCHIP_HH__
|
||||
|
||||
#include "mem/functional_mem/mmap_device.hh"
|
||||
#include "dev/tsunami.hh"
|
||||
|
||||
/*
|
||||
* Tsunami CChip
|
||||
*/
|
||||
class TsunamiCChip : public MmapDevice
|
||||
{
|
||||
public:
|
||||
|
||||
protected:
|
||||
Tsunami *tsunami;
|
||||
uint64_t dim[Tsunami::Max_CPUs];
|
||||
uint64_t dir[Tsunami::Max_CPUs];
|
||||
uint64_t drir;
|
||||
|
||||
public:
|
||||
TsunamiCChip(const std::string &name, Tsunami *t,
|
||||
Addr addr, Addr mask, MemoryController *mmu);
|
||||
|
||||
virtual Fault read(MemReqPtr req, uint8_t *data);
|
||||
virtual Fault write(MemReqPtr req, const uint8_t *data);
|
||||
|
||||
virtual void serialize(std::ostream &os);
|
||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
};
|
||||
|
||||
#endif // __TSUNAMI_CCHIP_HH__
|
||||
33
dev/tsunamireg.h
Normal file
33
dev/tsunamireg.h
Normal file
@@ -0,0 +1,33 @@
|
||||
|
||||
#ifndef __TSUNAMIREG_H__
|
||||
#define __TSUNAMIREG_H__
|
||||
|
||||
#define TSDEV_CC_CSR 0x00
|
||||
#define TSDEV_CC_MTR 0x01
|
||||
#define TSDEV_CC_MISC 0x02
|
||||
|
||||
#define TSDEV_CC_AAR0 0x04
|
||||
#define TSDEV_CC_AAR1 0x05
|
||||
#define TSDEV_CC_AAR2 0x06
|
||||
#define TSDEV_CC_AAR3 0x07
|
||||
#define TSDEV_CC_DIM0 0x08
|
||||
#define TSDEV_CC_DIM1 0x09
|
||||
#define TSDEV_CC_DIR0 0x0A
|
||||
#define TSDEV_CC_DIR1 0x0B
|
||||
#define TSDEV_CC_DRIR 0x0C
|
||||
#define TSDEV_CC_PRBEN 0x0D
|
||||
#define TSDEV_CC_IIC0 0x0E
|
||||
#define TSDEV_CC_IIC1 0x0F
|
||||
#define TSDEV_CC_MPR0 0x10
|
||||
#define TSDEV_CC_MPR1 0x11
|
||||
#define TSDEV_CC_MPR2 0x12
|
||||
#define TSDEV_CC_MPR3 0x13
|
||||
|
||||
#define TSDEV_CC_DIM2 0x18
|
||||
#define TSDEV_CC_DIM3 0x19
|
||||
#define TSDEV_CC_DIR2 0x1A
|
||||
#define TSDEV_CC_DIR3 0x1B
|
||||
#define TSDEV_CC_IIC2 0x1C
|
||||
#define TSDEV_CC_IIC3 0x1D
|
||||
|
||||
#endif // __TSUNAMIREG_H__
|
||||
Reference in New Issue
Block a user