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ARM: Generalize the saturation instruction bases for use in other instructions.

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This commit is contained in:
Gabe Black
2010-06-02 12:58:07 -05:00
parent a1208aa66d
commit cb2e3b0ace
4 changed files with 43 additions and 43 deletions
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8
src/arch/arm/insts/misc.cc
View File

@@ -155,23 +155,23 @@ RevOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
}
std::string
SatOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
RegImmRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
ccprintf(ss, ", #%d, ", satImm);
ccprintf(ss, ", #%d, ", imm);
printReg(ss, op1);
return ss.str();
}
std::string
SatShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printReg(ss, dest);
ccprintf(ss, ", #%d, ", satImm);
ccprintf(ss, ", #%d, ", imm);
printShiftOperand(ss, op1, true, shiftAmt, INTREG_ZERO, shiftType);
printReg(ss, op1);
return ss.str();

22
src/arch/arm/insts/misc.hh
View File

@@ -108,36 +108,36 @@ class RevOp : public PredOp
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class SatOp : public PredOp
class RegImmRegOp : public PredOp
{
protected:
IntRegIndex dest;
uint32_t satImm;
uint32_t imm;
IntRegIndex op1;
SatOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, uint32_t _satImm, IntRegIndex _op1) :
RegImmRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1) :
PredOp(mnem, _machInst, __opClass),
dest(_dest), satImm(_satImm), op1(_op1)
dest(_dest), imm(_imm), op1(_op1)
{}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class SatShiftOp : public PredOp
class RegImmRegShiftOp : public PredOp
{
protected:
IntRegIndex dest;
uint32_t satImm;
uint32_t imm;
IntRegIndex op1;
int32_t shiftAmt;
ArmShiftType shiftType;
SatShiftOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, uint32_t _satImm, IntRegIndex _op1,
int32_t _shiftAmt, ArmShiftType _shiftType) :
RegImmRegShiftOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1,
int32_t _shiftAmt, ArmShiftType _shiftType) :
PredOp(mnem, _machInst, __opClass),
dest(_dest), satImm(_satImm), op1(_op1),
dest(_dest), imm(_imm), op1(_op1),
shiftAmt(_shiftAmt), shiftType(_shiftType)
{}

36
src/arch/arm/isa/insts/misc.isa
View File

@@ -157,33 +157,33 @@ let {{
ssatCode = '''
int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
int32_t res;
if (satInt(res, operand, satImm))
if (satInt(res, operand, imm))
CondCodes = CondCodes | (1 << 27);
else
CondCodes = CondCodes;
Dest = res;
'''
ssatIop = InstObjParams("ssat", "Ssat", "SatShiftOp",
ssatIop = InstObjParams("ssat", "Ssat", "RegImmRegShiftOp",
{ "code": ssatCode,
"predicate_test": predicateTest }, [])
header_output += SatShiftOpDeclare.subst(ssatIop)
decoder_output += SatShiftOpConstructor.subst(ssatIop)
header_output += RegImmRegShiftOpDeclare.subst(ssatIop)
decoder_output += RegImmRegShiftOpConstructor.subst(ssatIop)
exec_output += PredOpExecute.subst(ssatIop)
usatCode = '''
int32_t operand = shift_rm_imm(Op1, shiftAmt, shiftType, 0);
int32_t res;
if (uSatInt(res, operand, satImm))
if (uSatInt(res, operand, imm))
CondCodes = CondCodes | (1 << 27);
else
CondCodes = CondCodes;
Dest = res;
'''
usatIop = InstObjParams("usat", "Usat", "SatShiftOp",
usatIop = InstObjParams("usat", "Usat", "RegImmRegShiftOp",
{ "code": usatCode,
"predicate_test": predicateTest }, [])
header_output += SatShiftOpDeclare.subst(usatIop)
decoder_output += SatShiftOpConstructor.subst(usatIop)
header_output += RegImmRegShiftOpDeclare.subst(usatIop)
decoder_output += RegImmRegShiftOpConstructor.subst(usatIop)
exec_output += PredOpExecute.subst(usatIop)
ssat16Code = '''
@@ -192,19 +192,19 @@ let {{
CondCodes = CondCodes;
int32_t argLow = sext<16>(bits(Op1, 15, 0));
int32_t argHigh = sext<16>(bits(Op1, 31, 16));
if (satInt(res, argLow, satImm))
if (satInt(res, argLow, imm))
CondCodes = CondCodes | (1 << 27);
replaceBits(resTemp, 15, 0, res);
if (satInt(res, argHigh, satImm))
if (satInt(res, argHigh, imm))
CondCodes = CondCodes | (1 << 27);
replaceBits(resTemp, 31, 16, res);
Dest = resTemp;
'''
ssat16Iop = InstObjParams("ssat16", "Ssat16", "SatOp",
ssat16Iop = InstObjParams("ssat16", "Ssat16", "RegImmRegOp",
{ "code": ssat16Code,
"predicate_test": predicateTest }, [])
header_output += SatOpDeclare.subst(ssat16Iop)
decoder_output += SatOpConstructor.subst(ssat16Iop)
header_output += RegImmRegOpDeclare.subst(ssat16Iop)
decoder_output += RegImmRegOpConstructor.subst(ssat16Iop)
exec_output += PredOpExecute.subst(ssat16Iop)
usat16Code = '''
@@ -213,18 +213,18 @@ let {{
CondCodes = CondCodes;
int32_t argLow = sext<16>(bits(Op1, 15, 0));
int32_t argHigh = sext<16>(bits(Op1, 31, 16));
if (uSatInt(res, argLow, satImm))
if (uSatInt(res, argLow, imm))
CondCodes = CondCodes | (1 << 27);
replaceBits(resTemp, 15, 0, res);
if (uSatInt(res, argHigh, satImm))
if (uSatInt(res, argHigh, imm))
CondCodes = CondCodes | (1 << 27);
replaceBits(resTemp, 31, 16, res);
Dest = resTemp;
'''
usat16Iop = InstObjParams("usat16", "Usat16", "SatOp",
usat16Iop = InstObjParams("usat16", "Usat16", "RegImmRegOp",
{ "code": usat16Code,
"predicate_test": predicateTest }, [])
header_output += SatOpDeclare.subst(usat16Iop)
decoder_output += SatOpConstructor.subst(usat16Iop)
header_output += RegImmRegOpDeclare.subst(usat16Iop)
decoder_output += RegImmRegOpConstructor.subst(usat16Iop)
exec_output += PredOpExecute.subst(usat16Iop)
}};

20
src/arch/arm/isa/templates/misc.isa
View File

@@ -120,52 +120,52 @@ def template RevOpConstructor {{
}
}};
def template SatOpDeclare {{
def template RegImmRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
protected:
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, uint32_t _satImm, IntRegIndex _op1);
IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1);
%(BasicExecDeclare)s
};
}};
def template SatOpConstructor {{
def template RegImmRegOpConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
uint32_t _satImm,
uint32_t _imm,
IntRegIndex _op1)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _satImm, _op1)
_dest, _imm, _op1)
{
%(constructor)s;
}
}};
def template SatShiftOpDeclare {{
def template RegImmRegShiftOpDeclare {{
class %(class_name)s : public %(base_class)s
{
protected:
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, uint32_t _satImm, IntRegIndex _op1,
IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1,
int32_t _shiftAmt, ArmShiftType _shiftType);
%(BasicExecDeclare)s
};
}};
def template SatShiftOpConstructor {{
def template RegImmRegShiftOpConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
uint32_t _satImm,
uint32_t _imm,
IntRegIndex _op1,
int32_t _shiftAmt,
ArmShiftType _shiftType)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _satImm, _op1, _shiftAmt, _shiftType)
_dest, _imm, _op1, _shiftAmt, _shiftType)
{
%(constructor)s;
}