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configs,tests: use Sequencer port connect methods

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This patch updates Ruby configuration scripts to use the functions
defined in the RubySequencer python object to connect to cpu ports.

Only the protocol-agnostic scripts were updated. Scripts that assume
a specific protocol (e.g. configs/example/apu_se.py, gpu tests, etc)
and scripts in which the obj connected to the RubySequencer is not a
BaseCPU (e.g. the tests scripts) were not changed as they require a
non-standard port wireup.

Change-Id: I1e931ff0fc93f393cb36fbb8769ea4b48e1a1e86
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31418
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Tiago Mück
2020-06-19 21:08:33 -05:00
parent 4f48530129
commit ca29eef37e
6 changed files with 6 additions and 50 deletions
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10
configs/learning_gem5/part3/msi_caches.py
View File

@@ -105,15 +105,7 @@ class MyCacheSystem(RubySystem):
# Connect the cpu's cache, interrupt, and TLB ports to Ruby
for i,cpu in enumerate(cpus):
cpu.icache_port = self.sequencers[i].slave
cpu.dcache_port = self.sequencers[i].slave
cpu.mmu.connectWalkerPorts(
self.sequencers[i].slave, self.sequencers[i].slave)
isa = buildEnv['TARGET_ISA']
if isa == 'x86':
cpu.interrupts[0].pio = self.sequencers[i].master
cpu.interrupts[0].int_master = self.sequencers[i].slave
cpu.interrupts[0].int_slave = self.sequencers[i].master
self.sequencers[i].connectCpuPorts(cpu)
class L1Cache(L1Cache_Controller):

10
configs/learning_gem5/part3/ruby_caches_MI_example.py
View File

@@ -103,15 +103,7 @@ class MyCacheSystem(RubySystem):
# Connect the cpu's cache, interrupt, and TLB ports to Ruby
for i,cpu in enumerate(cpus):
cpu.icache_port = self.sequencers[i].slave
cpu.dcache_port = self.sequencers[i].slave
cpu.mmu.connectWalkerPorts(
self.sequencers[i].slave, self.sequencers[i].slave)
isa = buildEnv['TARGET_ISA']
if isa == 'x86':
cpu.interrupts[0].pio = self.sequencers[i].master
cpu.interrupts[0].int_master = self.sequencers[i].slave
cpu.interrupts[0].int_slave = self.sequencers[i].master
self.sequencers[i].connectCpuPorts(cpu)
class L1Cache(L1Cache_Controller):