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configs,tests: use Sequencer port connect methods

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This patch updates Ruby configuration scripts to use the functions
defined in the RubySequencer python object to connect to cpu ports.

Only the protocol-agnostic scripts were updated. Scripts that assume
a specific protocol (e.g. configs/example/apu_se.py, gpu tests, etc)
and scripts in which the obj connected to the RubySequencer is not a
BaseCPU (e.g. the tests scripts) were not changed as they require a
non-standard port wireup.

Change-Id: I1e931ff0fc93f393cb36fbb8769ea4b48e1a1e86
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31418
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Tiago Mück
2020-06-19 21:08:33 -05:00
parent 4f48530129
commit ca29eef37e
6 changed files with 6 additions and 50 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
configs/example/fs.py
View File

@@ -172,17 +172,7 @@ def build_test_system(np):
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
cpu.mmu.connectWalkerPorts(
test_sys.ruby._cpu_ports[i].slave,
test_sys.ruby._cpu_ports[i].slave)
if buildEnv['TARGET_ISA'] in "x86":
cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
test_sys.ruby._cpu_ports[i].connectCpuPorts(cpu)
else:
if options.caches or options.l2cache:

9
configs/example/se.py
View File

@@ -260,14 +260,7 @@ if options.ruby:
system.cpu[i].createInterruptController()
# Connect the cpu's cache ports to Ruby
system.cpu[i].icache_port = ruby_port.slave
system.cpu[i].dcache_port = ruby_port.slave
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].interrupts[0].pio = ruby_port.master
system.cpu[i].interrupts[0].int_master = ruby_port.slave
system.cpu[i].interrupts[0].int_slave = ruby_port.master
system.cpu[i].mmu.connectWalkerPorts(
ruby_port.slave, ruby_port.slave)
ruby_port.connectCpuPorts(system.cpu[i])
else:
MemClass = Simulation.setMemClass(options)
system.membus = SystemXBar()

10
configs/learning_gem5/part3/msi_caches.py
View File

@@ -105,15 +105,7 @@ class MyCacheSystem(RubySystem):
# Connect the cpu's cache, interrupt, and TLB ports to Ruby
for i,cpu in enumerate(cpus):
cpu.icache_port = self.sequencers[i].slave
cpu.dcache_port = self.sequencers[i].slave
cpu.mmu.connectWalkerPorts(
self.sequencers[i].slave, self.sequencers[i].slave)
isa = buildEnv['TARGET_ISA']
if isa == 'x86':
cpu.interrupts[0].pio = self.sequencers[i].master
cpu.interrupts[0].int_master = self.sequencers[i].slave
cpu.interrupts[0].int_slave = self.sequencers[i].master
self.sequencers[i].connectCpuPorts(cpu)
class L1Cache(L1Cache_Controller):

10
configs/learning_gem5/part3/ruby_caches_MI_example.py
View File

@@ -103,15 +103,7 @@ class MyCacheSystem(RubySystem):
# Connect the cpu's cache, interrupt, and TLB ports to Ruby
for i,cpu in enumerate(cpus):
cpu.icache_port = self.sequencers[i].slave
cpu.dcache_port = self.sequencers[i].slave
cpu.mmu.connectWalkerPorts(
self.sequencers[i].slave, self.sequencers[i].slave)
isa = buildEnv['TARGET_ISA']
if isa == 'x86':
cpu.interrupts[0].pio = self.sequencers[i].master
cpu.interrupts[0].int_master = self.sequencers[i].slave
cpu.interrupts[0].int_slave = self.sequencers[i].master
self.sequencers[i].connectCpuPorts(cpu)
class L1Cache(L1Cache_Controller):

6
configs/ruby/Ruby.py
View File

@@ -226,11 +226,7 @@ def create_system(options, full_system, system, piobus = None, dma_ports = [],
# Connect the cpu sequencers and the piobus
if piobus != None:
for cpu_seq in cpu_sequencers:
cpu_seq.pio_master_port = piobus.slave
cpu_seq.mem_master_port = piobus.slave
if buildEnv['TARGET_ISA'] == "x86":
cpu_seq.pio_slave_port = piobus.master
cpu_seq.connectIOPorts(piobus)
ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks
ruby._cpu_ports = cpu_sequencers

9
tests/configs/pc-simple-timing-ruby.py
View File

@@ -78,14 +78,7 @@ for (i, cpu) in enumerate(system.cpu):
# create the interrupt controller
cpu.createInterruptController()
# Tie the cpu ports to the correct ruby system ports
cpu.icache_port = system.ruby._cpu_ports[i].slave
cpu.dcache_port = system.ruby._cpu_ports[i].slave
cpu.mmu.connectWalkerPorts(
system.ruby._cpu_ports[i].slave, system.ruby._cpu_ports[i].slave)
cpu.interrupts[0].pio = system.ruby._cpu_ports[i].master
cpu.interrupts[0].int_master = system.ruby._cpu_ports[i].slave
cpu.interrupts[0].int_slave = system.ruby._cpu_ports[i].master
system.ruby._cpu_ports[i].connectCpuPorts(cpu)
root = Root(full_system = True, system = system)
m5.ticks.setGlobalFrequency('1THz')