arch-x86: Fix style in arch/x86/types.hh.
Change-Id: I5e32eea9b843d4f68adf5430516d0636317c8a57 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40103 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabe.black@gmail.com>
This commit is contained in:
Gabe Black
@@ -48,336 +48,339 @@
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namespace X86ISA
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{
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//This really determines how many bytes are passed to the decoder.
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typedef uint64_t MachInst;
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enum Prefixes {
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NoOverride,
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ESOverride,
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CSOverride,
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SSOverride,
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DSOverride,
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FSOverride,
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GSOverride,
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RexPrefix,
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OperandSizeOverride,
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AddressSizeOverride,
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Lock,
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Rep,
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Repne,
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Vex2Prefix,
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Vex3Prefix,
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XopPrefix,
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};
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//This really determines how many bytes are passed to the decoder.
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typedef uint64_t MachInst;
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BitUnion8(LegacyPrefixVector)
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Bitfield<7, 4> decodeVal;
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Bitfield<7> repne;
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Bitfield<6> rep;
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Bitfield<5> lock;
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Bitfield<4> op;
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Bitfield<3> addr;
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//There can be only one segment override, so they share the
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//first 3 bits in the legacyPrefixes bitfield.
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Bitfield<2,0> seg;
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EndBitUnion(LegacyPrefixVector)
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enum Prefixes {
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NoOverride,
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ESOverride,
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CSOverride,
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SSOverride,
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DSOverride,
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FSOverride,
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GSOverride,
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RexPrefix,
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OperandSizeOverride,
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AddressSizeOverride,
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Lock,
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Rep,
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Repne,
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Vex2Prefix,
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Vex3Prefix,
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XopPrefix,
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};
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BitUnion8(ModRM)
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Bitfield<7,6> mod;
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Bitfield<5,3> reg;
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Bitfield<2,0> rm;
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EndBitUnion(ModRM)
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BitUnion8(LegacyPrefixVector)
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Bitfield<7, 4> decodeVal;
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Bitfield<7> repne;
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Bitfield<6> rep;
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Bitfield<5> lock;
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Bitfield<4> op;
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Bitfield<3> addr;
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//There can be only one segment override, so they share the
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//first 3 bits in the legacyPrefixes bitfield.
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Bitfield<2,0> seg;
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EndBitUnion(LegacyPrefixVector)
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BitUnion8(Sib)
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Bitfield<7,6> scale;
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Bitfield<5,3> index;
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Bitfield<2,0> base;
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EndBitUnion(Sib)
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BitUnion8(ModRM)
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Bitfield<7,6> mod;
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Bitfield<5,3> reg;
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Bitfield<2,0> rm;
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EndBitUnion(ModRM)
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BitUnion8(Rex)
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//This bit doesn't mean anything according to the ISA, but in
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//this implementation, it being set means an REX prefix was present.
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Bitfield<6> present;
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Bitfield<3> w;
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Bitfield<2> r;
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Bitfield<1> x;
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Bitfield<0> b;
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EndBitUnion(Rex)
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BitUnion8(Sib)
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Bitfield<7,6> scale;
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Bitfield<5,3> index;
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Bitfield<2,0> base;
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EndBitUnion(Sib)
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BitUnion8(Vex2Of3)
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// Inverted bits from the REX prefix.
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Bitfield<7> r;
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Bitfield<6> x;
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Bitfield<5> b;
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// Selector for what would be two or three byte opcode types.
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Bitfield<4, 0> m;
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EndBitUnion(Vex2Of3)
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BitUnion8(Rex)
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//This bit doesn't mean anything according to the ISA, but in
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//this implementation, it being set means an REX prefix was present.
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Bitfield<6> present;
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Bitfield<3> w;
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Bitfield<2> r;
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Bitfield<1> x;
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Bitfield<0> b;
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EndBitUnion(Rex)
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BitUnion8(Vex3Of3)
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// Bit from the REX prefix.
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Bitfield<7> w;
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// Inverted extra register index.
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Bitfield<6, 3> v;
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// Vector length specifier.
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Bitfield<2> l;
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// Implied 66, F2, or F3 opcode prefix.
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Bitfield<1, 0> p;
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EndBitUnion(Vex3Of3)
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BitUnion8(Vex2Of3)
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// Inverted bits from the REX prefix.
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Bitfield<7> r;
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Bitfield<6> x;
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Bitfield<5> b;
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// Selector for what would be two or three byte opcode types.
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Bitfield<4, 0> m;
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EndBitUnion(Vex2Of3)
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BitUnion8(Vex2Of2)
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// Inverted bit from the REX prefix.
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Bitfield<7> r;
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// Inverted extra register index.
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Bitfield<6, 3> v;
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// Vector length specifier
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Bitfield<2> l;
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// Implied 66, F2, or F3 opcode prefix.
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Bitfield<1, 0> p;
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EndBitUnion(Vex2Of2)
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BitUnion8(Vex3Of3)
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// Bit from the REX prefix.
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Bitfield<7> w;
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// Inverted extra register index.
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Bitfield<6, 3> v;
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// Vector length specifier.
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Bitfield<2> l;
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// Implied 66, F2, or F3 opcode prefix.
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Bitfield<1, 0> p;
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EndBitUnion(Vex3Of3)
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BitUnion8(VexInfo)
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// Extra register index.
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Bitfield<6, 3> v;
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// Vector length specifier.
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Bitfield<2> l;
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// Whether the VEX prefix was used.
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Bitfield<0> present;
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EndBitUnion(VexInfo)
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BitUnion8(Vex2Of2)
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// Inverted bit from the REX prefix.
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Bitfield<7> r;
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// Inverted extra register index.
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Bitfield<6, 3> v;
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// Vector length specifier
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Bitfield<2> l;
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// Implied 66, F2, or F3 opcode prefix.
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Bitfield<1, 0> p;
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EndBitUnion(Vex2Of2)
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enum OpcodeType {
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BadOpcode,
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OneByteOpcode,
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TwoByteOpcode,
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ThreeByte0F38Opcode,
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ThreeByte0F3AOpcode,
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};
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BitUnion8(VexInfo)
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// Extra register index.
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Bitfield<6, 3> v;
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// Vector length specifier.
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Bitfield<2> l;
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// Whether the VEX prefix was used.
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Bitfield<0> present;
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EndBitUnion(VexInfo)
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static inline const char *
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opcodeTypeToStr(OpcodeType type)
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enum OpcodeType {
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BadOpcode,
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OneByteOpcode,
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TwoByteOpcode,
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ThreeByte0F38Opcode,
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ThreeByte0F3AOpcode,
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};
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static inline const char *
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opcodeTypeToStr(OpcodeType type)
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{
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switch (type) {
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case BadOpcode:
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return "bad";
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case OneByteOpcode:
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return "one byte";
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case TwoByteOpcode:
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return "two byte";
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case ThreeByte0F38Opcode:
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return "three byte 0f38";
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case ThreeByte0F3AOpcode:
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return "three byte 0f3a";
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default:
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return "unrecognized!";
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}
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}
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BitUnion8(Opcode)
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Bitfield<7,3> top5;
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Bitfield<2,0> bottom3;
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EndBitUnion(Opcode)
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BitUnion8(OperatingMode)
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Bitfield<3> mode;
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Bitfield<2,0> submode;
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EndBitUnion(OperatingMode)
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enum X86Mode {
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LongMode,
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LegacyMode
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};
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enum X86SubMode {
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SixtyFourBitMode,
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CompatabilityMode,
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ProtectedMode,
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Virtual8086Mode,
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RealMode
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};
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//The intermediate structure used by the x86 decoder.
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struct ExtMachInst
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{
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void reset() { memset(static_cast<void *>(this), 0, sizeof(*this)); }
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//Prefixes
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LegacyPrefixVector legacy;
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Rex rex;
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VexInfo vex;
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//This holds all of the bytes of the opcode
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struct
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{
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switch (type) {
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case BadOpcode:
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return "bad";
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case OneByteOpcode:
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return "one byte";
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case TwoByteOpcode:
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return "two byte";
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case ThreeByte0F38Opcode:
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return "three byte 0f38";
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case ThreeByte0F3AOpcode:
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return "three byte 0f3a";
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default:
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return "unrecognized!";
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}
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OpcodeType type;
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//The main opcode byte. The highest addressed byte in the opcode.
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Opcode op;
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} opcode;
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//Modifier bytes
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ModRM modRM;
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Sib sib;
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//Immediate fields
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uint64_t immediate;
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uint64_t displacement;
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//The effective operand size.
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uint8_t opSize;
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//The effective address size.
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uint8_t addrSize;
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//The effective stack size.
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uint8_t stackSize;
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//The size of the displacement
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uint8_t dispSize;
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//Mode information
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OperatingMode mode;
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};
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inline static std::ostream &
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operator << (std::ostream &os, const ExtMachInst &emi)
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{
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ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t"
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"vex/xop = %#x,\n\t"
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"op = {\n\t\ttype = %s,\n\t\top = %#x,\n\t\t},\n\t"
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"modRM = %#x,\n\tsib = %#x,\n\t"
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"immediate = %#x,\n\tdisplacement = %#x\n\t"
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"dispSize = %d}\n",
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(uint8_t)emi.legacy, (uint8_t)emi.rex,
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(uint8_t)emi.vex,
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opcodeTypeToStr(emi.opcode.type), (uint8_t)emi.opcode.op,
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(uint8_t)emi.modRM, (uint8_t)emi.sib,
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emi.immediate, emi.displacement, emi.dispSize);
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return os;
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}
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inline static bool
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operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
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{
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if (emi1.legacy != emi2.legacy)
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return false;
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if (emi1.rex != emi2.rex)
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return false;
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if (emi1.vex != emi2.vex)
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return false;
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if (emi1.opcode.type != emi2.opcode.type)
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return false;
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if (emi1.opcode.op != emi2.opcode.op)
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return false;
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if (emi1.modRM != emi2.modRM)
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return false;
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if (emi1.sib != emi2.sib)
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return false;
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if (emi1.immediate != emi2.immediate)
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return false;
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if (emi1.displacement != emi2.displacement)
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return false;
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if (emi1.mode != emi2.mode)
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return false;
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if (emi1.opSize != emi2.opSize)
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return false;
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if (emi1.addrSize != emi2.addrSize)
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return false;
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if (emi1.stackSize != emi2.stackSize)
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return false;
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if (emi1.dispSize != emi2.dispSize)
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return false;
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return true;
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}
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class PCState : public GenericISA::UPCState<MachInst>
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{
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protected:
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typedef GenericISA::UPCState<MachInst> Base;
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uint8_t _size;
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public:
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void
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set(Addr val)
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{
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Base::set(val);
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_size = 0;
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}
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BitUnion8(Opcode)
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Bitfield<7,3> top5;
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Bitfield<2,0> bottom3;
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EndBitUnion(Opcode)
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PCState() {}
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PCState(Addr val) { set(val); }
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BitUnion8(OperatingMode)
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Bitfield<3> mode;
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Bitfield<2,0> submode;
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EndBitUnion(OperatingMode)
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enum X86Mode {
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LongMode,
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LegacyMode
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};
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enum X86SubMode {
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SixtyFourBitMode,
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CompatabilityMode,
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ProtectedMode,
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Virtual8086Mode,
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RealMode
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};
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//The intermediate structure used by the x86 decoder.
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struct ExtMachInst
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void
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setNPC(Addr val)
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{
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void reset() {
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memset(static_cast<void *>(this), 0, sizeof(*this));
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}
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//Prefixes
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LegacyPrefixVector legacy;
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Rex rex;
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VexInfo vex;
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//This holds all of the bytes of the opcode
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struct
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{
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OpcodeType type;
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//The main opcode byte. The highest addressed byte in the opcode.
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Opcode op;
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} opcode;
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//Modifier bytes
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ModRM modRM;
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Sib sib;
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//Immediate fields
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uint64_t immediate;
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uint64_t displacement;
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//The effective operand size.
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uint8_t opSize;
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//The effective address size.
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uint8_t addrSize;
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//The effective stack size.
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uint8_t stackSize;
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//The size of the displacement
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uint8_t dispSize;
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//Mode information
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OperatingMode mode;
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};
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inline static std::ostream &
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operator << (std::ostream & os, const ExtMachInst & emi)
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{
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ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t"
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"vex/xop = %#x,\n\t"
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"op = {\n\t\ttype = %s,\n\t\top = %#x,\n\t\t},\n\t"
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"modRM = %#x,\n\tsib = %#x,\n\t"
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"immediate = %#x,\n\tdisplacement = %#x\n\t"
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"dispSize = %d}\n",
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(uint8_t)emi.legacy, (uint8_t)emi.rex,
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(uint8_t)emi.vex,
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opcodeTypeToStr(emi.opcode.type), (uint8_t)emi.opcode.op,
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(uint8_t)emi.modRM, (uint8_t)emi.sib,
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emi.immediate, emi.displacement, emi.dispSize);
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return os;
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Base::setNPC(val);
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_size = 0;
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}
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inline static bool
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operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
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uint8_t size() const { return _size; }
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void size(uint8_t newSize) { _size = newSize; }
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bool
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branching() const
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{
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if (emi1.legacy != emi2.legacy)
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return false;
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if (emi1.rex != emi2.rex)
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return false;
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if (emi1.vex != emi2.vex)
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return false;
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if (emi1.opcode.type != emi2.opcode.type)
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return false;
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if (emi1.opcode.op != emi2.opcode.op)
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return false;
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if (emi1.modRM != emi2.modRM)
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return false;
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if (emi1.sib != emi2.sib)
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return false;
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if (emi1.immediate != emi2.immediate)
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return false;
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if (emi1.displacement != emi2.displacement)
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return false;
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if (emi1.mode != emi2.mode)
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return false;
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if (emi1.opSize != emi2.opSize)
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return false;
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if (emi1.addrSize != emi2.addrSize)
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return false;
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if (emi1.stackSize != emi2.stackSize)
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return false;
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if (emi1.dispSize != emi2.dispSize)
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return false;
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return true;
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return (this->npc() != this->pc() + size()) ||
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(this->nupc() != this->upc() + 1);
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}
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class PCState : public GenericISA::UPCState<MachInst>
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void
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advance()
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{
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protected:
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typedef GenericISA::UPCState<MachInst> Base;
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Base::advance();
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_size = 0;
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}
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uint8_t _size;
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void
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uEnd()
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{
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Base::uEnd();
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_size = 0;
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}
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||||
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public:
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void
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set(Addr val)
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{
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Base::set(val);
|
||||
_size = 0;
|
||||
}
|
||||
void
|
||||
serialize(CheckpointOut &cp) const
|
||||
{
|
||||
Base::serialize(cp);
|
||||
SERIALIZE_SCALAR(_size);
|
||||
}
|
||||
|
||||
PCState() {}
|
||||
PCState(Addr val) { set(val); }
|
||||
|
||||
void
|
||||
setNPC(Addr val)
|
||||
{
|
||||
Base::setNPC(val);
|
||||
_size = 0;
|
||||
}
|
||||
|
||||
uint8_t size() const { return _size; }
|
||||
void size(uint8_t newSize) { _size = newSize; }
|
||||
|
||||
bool
|
||||
branching() const
|
||||
{
|
||||
return (this->npc() != this->pc() + size()) ||
|
||||
(this->nupc() != this->upc() + 1);
|
||||
}
|
||||
|
||||
void
|
||||
advance()
|
||||
{
|
||||
Base::advance();
|
||||
_size = 0;
|
||||
}
|
||||
|
||||
void
|
||||
uEnd()
|
||||
{
|
||||
Base::uEnd();
|
||||
_size = 0;
|
||||
}
|
||||
|
||||
void
|
||||
serialize(CheckpointOut &cp) const
|
||||
{
|
||||
Base::serialize(cp);
|
||||
SERIALIZE_SCALAR(_size);
|
||||
}
|
||||
|
||||
void
|
||||
unserialize(CheckpointIn &cp)
|
||||
{
|
||||
Base::unserialize(cp);
|
||||
UNSERIALIZE_SCALAR(_size);
|
||||
}
|
||||
};
|
||||
void
|
||||
unserialize(CheckpointIn &cp)
|
||||
{
|
||||
Base::unserialize(cp);
|
||||
UNSERIALIZE_SCALAR(_size);
|
||||
}
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
namespace std {
|
||||
template<>
|
||||
struct hash<X86ISA::ExtMachInst> {
|
||||
size_t operator()(const X86ISA::ExtMachInst &emi) const {
|
||||
return (((uint64_t)emi.legacy << 48) |
|
||||
((uint64_t)emi.rex << 40) |
|
||||
((uint64_t)emi.vex << 32) |
|
||||
((uint64_t)emi.modRM << 24) |
|
||||
((uint64_t)emi.sib << 16) |
|
||||
((uint64_t)emi.opcode.type << 8) |
|
||||
((uint64_t)emi.opcode.op)) ^
|
||||
emi.immediate ^ emi.displacement ^
|
||||
emi.mode ^
|
||||
emi.opSize ^ emi.addrSize ^
|
||||
emi.stackSize ^ emi.dispSize;
|
||||
};
|
||||
namespace std
|
||||
{
|
||||
|
||||
template<>
|
||||
struct hash<X86ISA::ExtMachInst>
|
||||
{
|
||||
size_t
|
||||
operator()(const X86ISA::ExtMachInst &emi) const
|
||||
{
|
||||
return (((uint64_t)emi.legacy << 48) |
|
||||
((uint64_t)emi.rex << 40) |
|
||||
((uint64_t)emi.vex << 32) |
|
||||
((uint64_t)emi.modRM << 24) |
|
||||
((uint64_t)emi.sib << 16) |
|
||||
((uint64_t)emi.opcode.type << 8) |
|
||||
((uint64_t)emi.opcode.op)) ^
|
||||
emi.immediate ^ emi.displacement ^
|
||||
emi.mode ^
|
||||
emi.opSize ^ emi.addrSize ^
|
||||
emi.stackSize ^ emi.dispSize;
|
||||
};
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
// These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR
|
||||
// and UNSERIALIZE_SCALAR.
|
||||
template <>
|
||||
void
|
||||
paramOut(CheckpointOut &cp, const std::string &name,
|
||||
const X86ISA::ExtMachInst &machInst);
|
||||
void paramOut(CheckpointOut &cp, const std::string &name,
|
||||
const X86ISA::ExtMachInst &machInst);
|
||||
template <>
|
||||
void
|
||||
paramIn(CheckpointIn &cp, const std::string &name,
|
||||
void paramIn(CheckpointIn &cp, const std::string &name,
|
||||
X86ISA::ExtMachInst &machInst);
|
||||
|
||||
#endif // __ARCH_X86_TYPES_HH__
|
||||
|
||||
Reference in New Issue
Block a user