arch: Introduce a base class for ISA classes.

These don't have anything in them at the moment since making some ISA
methods virtual and not inlined will likely add overhead, specifically
the ones for flattening registers. Some code may need to be rearranged
to minimize that overhead before the ISA objects can be truly put
behind a generic interface.

Change-Id: Ie36a771e977535a7996fdff701ce202bb95c8c58
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25007
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

src/arch/generic/SConscript

@@ -47,6 +47,7 @@ Source('decode_cache.cc')
 Source('mmapped_ipr.cc')
 
 SimObject('BaseInterrupts.py')
+SimObject('BaseISA.py')
 SimObject('BaseTLB.py')
 SimObject('ISACommon.py')