derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-arm: Clear unused WARN_NOT_FAIL flag for AArch64 CMOs

Browse Source 
The following AArch64 CMOs were flagged as warnNotFail even
if they are actually implemented and there is no reason
for them to fail:

MISCREG_DC_IVAC_Xt
MISCREG_DC_ZVA_Xt
MISCREG_DC_CVAC_Xt
MISCREG_DC_CVAU_Xt
MISCREG_DC_CIVAC_Xt

This is likely coming from AArch32 (those CMOs are unimplemented in
AArch32).

Please note: this patch is not changing anything behaviorally; the
warnOnFail flag is not considered in AArch64 unless the unimplemented
flag is also set (and this was not the case for those CMOs)

Change-Id: I40396016703b9eb48f69b0eb710d077f8c2b146b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61685
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2022-07-20 09:06:09 +01:00
parent ce7448b53e
commit c7b7314d8b
1 changed files with 0 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/arch/arm/regs/misc.cc
View File

@@ -3937,7 +3937,6 @@ ISA::initializeMiscRegMetadata()
.faultWrite(EL1, faultPouEL1)
.writes(1).exceptUserMode();
InitReg(MISCREG_DC_IVAC_Xt)
.warnNotFail()
.faultWrite(EL1, HCR_TRAP(tpc))
.writes(1).exceptUserMode();
InitReg(MISCREG_DC_ISW_Xt)
@@ -3965,7 +3964,6 @@ ISA::initializeMiscRegMetadata()
.faultWrite(EL1, HCR_TRAP(tsw))
.writes(1).exceptUserMode();
InitReg(MISCREG_DC_ZVA_Xt)
.warnNotFail()
.writes(1)
.faultWrite(EL0, faultDczvaEL0)
.faultWrite(EL1, HCR_TRAP(tdz));
@@ -3974,17 +3972,14 @@ ISA::initializeMiscRegMetadata()
.faultWrite(EL1, faultPouEL1)
.writes(1);
InitReg(MISCREG_DC_CVAC_Xt)
.warnNotFail()
.faultWrite(EL0, faultCvacEL0)
.faultWrite(EL1, HCR_TRAP(tpc))
.writes(1);
InitReg(MISCREG_DC_CVAU_Xt)
.warnNotFail()
.faultWrite(EL0, faultPouEL0)
.faultWrite(EL1, faultPouEL1)
.writes(1);
InitReg(MISCREG_DC_CIVAC_Xt)
.warnNotFail()
.faultWrite(EL0, faultCvacEL0)
.faultWrite(EL1, HCR_TRAP(tpc))
.writes(1);