Fix handling of rpcc in full-system mode.

arch/alpha/ev5.cc:
    Handle writing IPR_CC and IPR_CC_CTL slightly more intelligently.
    (Very slightly).
arch/alpha/isa_desc:
    Upper half of rpcc result comes from value written
    to IPR_CC, not actual cycle counter.

--HG--
extra : convert_revision : 7161989db8a3f040d0558e2e5a1a162ed1cb4125

arch/alpha/ev5.cc

@@ -329,13 +329,25 @@ ExecContext::setIpr(int idx, uint64_t val)
       case AlphaISA::IPR_PAL_BASE:
       case AlphaISA::IPR_IC_PERR_STAT:
       case AlphaISA::IPR_DC_PERR_STAT:
-      case AlphaISA::IPR_CC_CTL:
-      case AlphaISA::IPR_CC:
       case AlphaISA::IPR_PMCTR:
         // write entire quad w/ no side-effect
         ipr[idx] = val;
         break;
 
+      case AlphaISA::IPR_CC_CTL:
+        // This IPR resets the cycle counter.  We assume this only
+        // happens once... let's verify that.
+        assert(ipr[idx] == 0);
+        ipr[idx] = 1;
+        break;
+
+      case AlphaISA::IPR_CC:
+        // This IPR only writes the upper 64 bits.  It's ok to write
+        // all 64 here since we mask out the lower 32 in rpcc (see
+        // isa_desc).
+        ipr[idx] = val;
+        break;
+
       case AlphaISA::IPR_PALtemp23:
         // write entire quad w/ no side-effect
         ipr[idx] = val;

arch/alpha/isa_desc

@@ -2388,7 +2388,14 @@ decode OPCODE default Unknown::unknown() {
 	}
 
 	format BasicOperate {
-	    0xc000: rpcc({{ Ra = curTick; }});
+	    0xc000: rpcc({{
+#ifdef FULL_SYSTEM
+		uint64_t cc = xc->readIpr(AlphaISA::IPR_CC, fault);
+		Ra = (cc<63:32> | curTick<31:0>);
+#else
+		Ra = curTick;
+#endif
+	    }});
 
 	    // All of the barrier instructions below do nothing in
 	    // their execute() methods (hence the empty code blocks).