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ruby: Fix MOESI_hammer cache profiler calls for L2 misses

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This commit is contained in:
Brad Beckmann
2010-03-21 21:22:20 -07:00
parent 1765badda2
commit c48a735336
1 changed files with 4 additions and 1 deletions
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5
src/mem/protocol/MOESI_hammer-cache.sm
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@@ -683,7 +683,8 @@ machine(L1Cache, "AMD Hammer-like protocol")
L1IcacheMemory.profileMiss(in_msg);
} else if (L1DcacheMemory.isTagPresent(address)) {
L1DcacheMemory.profileMiss(in_msg);
} else {
}
if (L2cacheMemory.isTagPresent(address) == false) {
L2cacheMemory.profileMiss(in_msg);
}
}
@@ -724,12 +725,14 @@ machine(L1Cache, "AMD Hammer-like protocol")
transition({I, S, O, M, MM}, L2_to_L1D) {
ii_allocateL1DCacheBlock;
tt_copyFromL2toL1; // Not really needed for state I
uu_profileMiss;
rr_deallocateL2CacheBlock;
}
transition({I, S, O, M, MM}, L2_to_L1I) {
jj_allocateL1ICacheBlock;
tt_copyFromL2toL1; // Not really needed for state I
uu_profileMiss;
rr_deallocateL2CacheBlock;
}