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cpu: Fix coding style (byteEnable->byte_enable)

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Change-Id: I2206559c6c2a6e6a0452e9c7d9964792afa9f358
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23282
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
This commit is contained in:
Giacomo Travaglini
2019-11-27 15:48:22 +00:00
parent f73caae20f
commit c3bd8eb121
16 changed files with 71 additions and 70 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
src/cpu/base_dyn_inst.hh
View File

@@ -304,11 +304,11 @@ class BaseDynInst : public ExecContext, public RefCounted
}
Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
const std::vector<bool>& byteEnable = std::vector<bool>());
const std::vector<bool>& byte_enable = std::vector<bool>());
Fault writeMem(uint8_t *data, unsigned size, Addr addr,
Request::Flags flags, uint64_t *res,
const std::vector<bool>& byteEnable = std::vector<bool>());
const std::vector<bool>& byte_enable = std::vector<bool>());
Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
AtomicOpFunctorPtr amo_op);
@@ -963,25 +963,26 @@ template<class Impl>
Fault
BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
Request::Flags flags,
const std::vector<bool>& byteEnable)
const std::vector<bool>& byte_enable)
{
assert(byteEnable.empty() || byteEnable.size() == size);
assert(byte_enable.empty() || byte_enable.size() == size);
return cpu->pushRequest(
dynamic_cast<typename DynInstPtr::PtrType>(this),
/* ld */ true, nullptr, size, addr, flags, nullptr, nullptr,
byteEnable);
byte_enable);
}
template<class Impl>
Fault
BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
Request::Flags flags, uint64_t *res,
const std::vector<bool>& byteEnable)
const std::vector<bool>& byte_enable)
{
assert(byteEnable.empty() || byteEnable.size() == size);
assert(byte_enable.empty() || byte_enable.size() == size);
return cpu->pushRequest(
dynamic_cast<typename DynInstPtr::PtrType>(this),
/* st */ false, data, size, addr, flags, res, nullptr, byteEnable);
/* st */ false, data, size, addr, flags, res, nullptr,
byte_enable);
}
template<class Impl>

12
src/cpu/checker/cpu.cc
View File

@@ -176,9 +176,9 @@ CheckerCPU::genMemFragmentRequest(Addr frag_addr, int size,
Fault
CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size,
Request::Flags flags,
const std::vector<bool>& byteEnable)
const std::vector<bool>& byte_enable)
{
assert(byteEnable.empty() || byteEnable.size() == size);
assert(byte_enable.empty() || byte_enable.size() == size);
Fault fault = NoFault;
bool checked_flags = false;
@@ -193,7 +193,7 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size,
// Need to account for multiple accesses like the Atomic and TimingSimple
while (1) {
RequestPtr mem_req = genMemFragmentRequest(frag_addr, size, flags,
byteEnable, frag_size,
byte_enable, frag_size,
size_left);
predicate = (mem_req != nullptr);
@@ -260,9 +260,9 @@ CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size,
Fault
CheckerCPU::writeMem(uint8_t *data, unsigned size,
Addr addr, Request::Flags flags, uint64_t *res,
const std::vector<bool>& byteEnable)
const std::vector<bool>& byte_enable)
{
assert(byteEnable.empty() || byteEnable.size() == size);
assert(byte_enable.empty() || byte_enable.size() == size);
Fault fault = NoFault;
bool checked_flags = false;
@@ -278,7 +278,7 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size,
// Need to account for a multiple access like Atomic and Timing CPUs
while (1) {
RequestPtr mem_req = genMemFragmentRequest(frag_addr, size, flags,
byteEnable, frag_size,
byte_enable, frag_size,
size_left);
predicate = (mem_req != nullptr);

4
src/cpu/checker/cpu.hh
View File

@@ -556,12 +556,12 @@ class CheckerCPU : public BaseCPU, public ExecContext
Fault readMem(Addr addr, uint8_t *data, unsigned size,
Request::Flags flags,
const std::vector<bool>& byteEnable = std::vector<bool>())
const std::vector<bool>& byte_enable = std::vector<bool>())
override;
Fault writeMem(uint8_t *data, unsigned size, Addr addr,
Request::Flags flags, uint64_t *res,
const std::vector<bool>& byteEnable = std::vector<bool>())
const std::vector<bool>& byte_enable = std::vector<bool>())
override;
Fault amoMem(Addr addr, uint8_t* data, unsigned size,

6
src/cpu/exec_context.hh
View File

@@ -236,7 +236,7 @@ class ExecContext {
*/
virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
Request::Flags flags,
const std::vector<bool>& byteEnable = std::vector<bool>())
const std::vector<bool>& byte_enable = std::vector<bool>())
{
panic("ExecContext::readMem() should be overridden\n");
}
@@ -250,7 +250,7 @@ class ExecContext {
*/
virtual Fault initiateMemRead(Addr addr, unsigned int size,
Request::Flags flags,
const std::vector<bool>& byteEnable = std::vector<bool>())
const std::vector<bool>& byte_enable = std::vector<bool>())
{
panic("ExecContext::initiateMemRead() should be overridden\n");
}
@@ -261,7 +261,7 @@ class ExecContext {
*/
virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
Request::Flags flags, uint64_t *res,
const std::vector<bool>& byteEnable =
const std::vector<bool>& byte_enable =
std::vector<bool>()) = 0;
/**

14
src/cpu/minor/exec_context.hh
View File

@@ -113,23 +113,23 @@ class ExecContext : public ::ExecContext
Fault
initiateMemRead(Addr addr, unsigned int size,
Request::Flags flags,
const std::vector<bool>& byteEnable = std::vector<bool>())
override
const std::vector<bool>& byte_enable =
std::vector<bool>()) override
{
assert(byteEnable.empty() || byteEnable.size() == size);
assert(byte_enable.empty() || byte_enable.size() == size);
return execute.getLSQ().pushRequest(inst, true /* load */, nullptr,
size, addr, flags, nullptr, nullptr, byteEnable);
size, addr, flags, nullptr, nullptr, byte_enable);
}
Fault
writeMem(uint8_t *data, unsigned int size, Addr addr,
Request::Flags flags, uint64_t *res,
const std::vector<bool>& byteEnable = std::vector<bool>())
const std::vector<bool>& byte_enable = std::vector<bool>())
override
{
assert(byteEnable.empty() || byteEnable.size() == size);
assert(byte_enable.empty() || byte_enable.size() == size);
return execute.getLSQ().pushRequest(inst, false /* store */, data,
size, addr, flags, res, nullptr, byteEnable);
size, addr, flags, res, nullptr, byte_enable);
}
Fault

10
src/cpu/minor/lsq.cc
View File

@@ -295,9 +295,9 @@ LSQ::SingleDataRequest::startAddrTranslation()
ThreadContext *thread = port.cpu.getContext(
inst->id.threadId);
const auto &byteEnable = request->getByteEnable();
if (byteEnable.size() == 0 ||
isAnyActiveElement(byteEnable.cbegin(), byteEnable.cend())) {
const auto &byte_enable = request->getByteEnable();
if (byte_enable.size() == 0 ||
isAnyActiveElement(byte_enable.cbegin(), byte_enable.cend())) {
port.numAccessesInDTLB++;
setState(LSQ::LSQRequest::InTranslation);
@@ -1574,7 +1574,7 @@ Fault
LSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
unsigned int size, Addr addr, Request::Flags flags,
uint64_t *res, AtomicOpFunctorPtr amo_op,
const std::vector<bool>& byteEnable)
const std::vector<bool>& byte_enable)
{
assert(inst->translationFault == NoFault || inst->inLSQ);
@@ -1636,7 +1636,7 @@ LSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
addr, size, flags, cpu.dataMasterId(),
/* I've no idea why we need the PC, but give it */
inst->pc.instAddr(), std::move(amo_op));
request->request->setByteEnable(byteEnable);
request->request->setByteEnable(byte_enable);
requests.push(request);
inst->inLSQ = true;

2
src/cpu/minor/lsq.hh
View File

@@ -709,7 +709,7 @@ class LSQ : public Named
Fault pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
unsigned int size, Addr addr, Request::Flags flags,
uint64_t *res, AtomicOpFunctorPtr amo_op,
const std::vector<bool>& byteEnable =
const std::vector<bool>& byte_enable =
std::vector<bool>());
/** Push a predicate failed-representing request into the queues just

4
src/cpu/o3/cpu.hh
View File

@@ -714,12 +714,12 @@ class FullO3CPU : public BaseO3CPU
Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
unsigned int size, Addr addr, Request::Flags flags,
uint64_t *res, AtomicOpFunctorPtr amo_op = nullptr,
const std::vector<bool>& byteEnable =
const std::vector<bool>& byte_enable =
std::vector<bool>())
{
return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr,
flags, res, std::move(amo_op), byteEnable);
flags, res, std::move(amo_op), byte_enable);
}
/** CPU read function, forwards read to LSQ. */

12
src/cpu/o3/lsq.hh
View File

@@ -406,16 +406,16 @@ class LSQ
*/
void
addRequest(Addr addr, unsigned size,
const std::vector<bool>& byteEnable)
const std::vector<bool>& byte_enable)
{
if (byteEnable.empty() ||
isAnyActiveElement(byteEnable.begin(), byteEnable.end())) {
if (byte_enable.empty() ||
isAnyActiveElement(byte_enable.begin(), byte_enable.end())) {
auto request = std::make_shared<Request>(_inst->getASID(),
addr, size, _flags, _inst->masterId(),
_inst->instAddr(), _inst->contextId(),
std::move(_amo_op));
if (!byteEnable.empty()) {
request->setByteEnable(byteEnable);
if (!byte_enable.empty()) {
request->setByteEnable(byte_enable);
}
_requests.push_back(request);
}
@@ -1040,7 +1040,7 @@ class LSQ
Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
unsigned int size, Addr addr, Request::Flags flags,
uint64_t *res, AtomicOpFunctorPtr amo_op,
const std::vector<bool>& byteEnable);
const std::vector<bool>& byte_enable);
/** The CPU pointer. */
O3CPU *cpu;

6
src/cpu/o3/lsq_impl.hh
View File

@@ -688,7 +688,7 @@ Fault
LSQ<Impl>::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
unsigned int size, Addr addr, Request::Flags flags,
uint64_t *res, AtomicOpFunctorPtr amo_op,
const std::vector<bool>& byteEnable)
const std::vector<bool>& byte_enable)
{
// This comming request can be either load, store or atomic.
// Atomic request has a corresponding pointer to its atomic memory
@@ -720,8 +720,8 @@ LSQ<Impl>::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
size, flags, data, res, std::move(amo_op));
}
assert(req);
if (!byteEnable.empty()) {
req->_byteEnable = byteEnable;
if (!byte_enable.empty()) {
req->_byteEnable = byte_enable;
}
inst->setRequest();
req->taskId(cpu->taskId());

10
src/cpu/simple/atomic.cc
View File

@@ -371,7 +371,7 @@ AtomicSimpleCPU::genMemFragmentRequest(const RequestPtr& req, Addr frag_addr,
Fault
AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size,
Request::Flags flags,
const std::vector<bool>& byteEnable)
const std::vector<bool>& byte_enable)
{
SimpleExecContext& t_info = *threadInfo[curThread];
SimpleThread* thread = t_info.thread;
@@ -394,7 +394,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size,
while (1) {
predicate = genMemFragmentRequest(req, frag_addr, size, flags,
byteEnable, frag_size, size_left);
byte_enable, frag_size, size_left);
// translate to physical address
if (predicate) {
@@ -453,7 +453,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size,
Fault
AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr,
Request::Flags flags, uint64_t *res,
const std::vector<bool>& byteEnable)
const std::vector<bool>& byte_enable)
{
SimpleExecContext& t_info = *threadInfo[curThread];
SimpleThread* thread = t_info.thread;
@@ -485,7 +485,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr,
while (1) {
predicate = genMemFragmentRequest(req, frag_addr, size, flags,
byteEnable, frag_size, size_left);
byte_enable, frag_size, size_left);
// translate to physical address
if (predicate)
@@ -541,7 +541,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr,
if (fault != NoFault || size_left == 0)
{
if (req->isLockedRMW() && fault == NoFault) {
assert(byteEnable.empty());
assert(byte_enable.empty());
locked = false;
}

4
src/cpu/simple/atomic.hh
View File

@@ -218,12 +218,12 @@ class AtomicSimpleCPU : public BaseSimpleCPU
Fault readMem(Addr addr, uint8_t *data, unsigned size,
Request::Flags flags,
const std::vector<bool>& byteEnable = std::vector<bool>())
const std::vector<bool>& byte_enable = std::vector<bool>())
override;
Fault writeMem(uint8_t *data, unsigned size,
Addr addr, Request::Flags flags, uint64_t *res,
const std::vector<bool>& byteEnable = std::vector<bool>())
const std::vector<bool>& byte_enable = std::vector<bool>())
override;
Fault amoMem(Addr addr, uint8_t* data, unsigned size,

6
src/cpu/simple/base.hh
View File

@@ -144,19 +144,19 @@ class BaseSimpleCPU : public BaseCPU
virtual Fault readMem(Addr addr, uint8_t* data, unsigned size,
Request::Flags flags,
const std::vector<bool>& byteEnable =
const std::vector<bool>& byte_enable =
std::vector<bool>())
{ panic("readMem() is not implemented\n"); }
virtual Fault initiateMemRead(Addr addr, unsigned size,
Request::Flags flags,
const std::vector<bool>& byteEnable =
const std::vector<bool>& byte_enable =
std::vector<bool>())
{ panic("initiateMemRead() is not implemented\n"); }
virtual Fault writeMem(uint8_t* data, unsigned size, Addr addr,
Request::Flags flags, uint64_t* res,
const std::vector<bool>& byteEnable =
const std::vector<bool>& byte_enable =
std::vector<bool>())
{ panic("writeMem() is not implemented\n"); }

18
src/cpu/simple/exec_context.hh
View File

@@ -437,31 +437,31 @@ class SimpleExecContext : public ExecContext {
Fault
readMem(Addr addr, uint8_t *data, unsigned int size,
Request::Flags flags,
const std::vector<bool>& byteEnable = std::vector<bool>())
const std::vector<bool>& byte_enable = std::vector<bool>())
override
{
assert(byteEnable.empty() || byteEnable.size() == size);
return cpu->readMem(addr, data, size, flags, byteEnable);
assert(byte_enable.empty() || byte_enable.size() == size);
return cpu->readMem(addr, data, size, flags, byte_enable);
}
Fault
initiateMemRead(Addr addr, unsigned int size,
Request::Flags flags,
const std::vector<bool>& byteEnable = std::vector<bool>())
const std::vector<bool>& byte_enable = std::vector<bool>())
override
{
assert(byteEnable.empty() || byteEnable.size() == size);
return cpu->initiateMemRead(addr, size, flags, byteEnable);
assert(byte_enable.empty() || byte_enable.size() == size);
return cpu->initiateMemRead(addr, size, flags, byte_enable);
}
Fault
writeMem(uint8_t *data, unsigned int size, Addr addr,
Request::Flags flags, uint64_t *res,
const std::vector<bool>& byteEnable = std::vector<bool>())
const std::vector<bool>& byte_enable = std::vector<bool>())
override
{
assert(byteEnable.empty() || byteEnable.size() == size);
return cpu->writeMem(data, size, addr, flags, res, byteEnable);
assert(byte_enable.empty() || byte_enable.size() == size);
return cpu->writeMem(data, size, addr, flags, res, byte_enable);
}
Fault amoMem(Addr addr, uint8_t *data, unsigned int size,

12
src/cpu/simple/timing.cc
View File

@@ -418,7 +418,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
Fault
TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size,
Request::Flags flags,
const std::vector<bool>& byteEnable)
const std::vector<bool>& byte_enable)
{
SimpleExecContext &t_info = *threadInfo[curThread];
SimpleThread* thread = t_info.thread;
@@ -435,8 +435,8 @@ TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size,
RequestPtr req = std::make_shared<Request>(
asid, addr, size, flags, dataMasterId(), pc,
thread->contextId());
if (!byteEnable.empty()) {
req->setByteEnable(byteEnable);
if (!byte_enable.empty()) {
req->setByteEnable(byte_enable);
}
req->taskId(taskId());
@@ -496,7 +496,7 @@ TimingSimpleCPU::handleWritePacket()
Fault
TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
Addr addr, Request::Flags flags, uint64_t *res,
const std::vector<bool>& byteEnable)
const std::vector<bool>& byte_enable)
{
SimpleExecContext &t_info = *threadInfo[curThread];
SimpleThread* thread = t_info.thread;
@@ -521,8 +521,8 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
RequestPtr req = std::make_shared<Request>(
asid, addr, size, flags, dataMasterId(), pc,
thread->contextId());
if (!byteEnable.empty()) {
req->setByteEnable(byteEnable);
if (!byte_enable.empty()) {
req->setByteEnable(byte_enable);
}
req->taskId(taskId());

4
src/cpu/simple/timing.hh
View File

@@ -284,12 +284,12 @@ class TimingSimpleCPU : public BaseSimpleCPU
Fault initiateMemRead(Addr addr, unsigned size,
Request::Flags flags,
const std::vector<bool>& byteEnable =std::vector<bool>())
const std::vector<bool>& byte_enable =std::vector<bool>())
override;
Fault writeMem(uint8_t *data, unsigned size,
Addr addr, Request::Flags flags, uint64_t *res,
const std::vector<bool>& byteEnable = std::vector<bool>())
const std::vector<bool>& byte_enable = std::vector<bool>())
override;
Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,