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learning-gem5: update port terminology

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Change-Id: I0ca705cf93396b5c34a0ac4dce30411c5c866733
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32310
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Emily Brickey
2020-08-04 12:04:03 -07:00
committed by Shivani Parekh
parent 4810c36401
commit c02599a70d
4 changed files with 22 additions and 22 deletions
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src/learning_gem5/part2/SimpleCache.py
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@@ -36,7 +36,7 @@ class SimpleCache(ClockedObject):
# Vector port example. Both the instruction and data ports connect to this
# port which is automatically split out into two ports.
cpu_side = VectorSlavePort("CPU side port, receives requests")
mem_side = MasterPort("Memory side port, sends requests")
mem_side = RequestPort("Memory side port, sends requests")
latency = Param.Cycles(1, "Cycles taken on a hit or to resolve a miss")