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learning-gem5: update port terminology

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Change-Id: I0ca705cf93396b5c34a0ac4dce30411c5c866733
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32310
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Emily Brickey
2020-08-04 12:04:03 -07:00
committed by Shivani Parekh
parent 4810c36401
commit c02599a70d
4 changed files with 22 additions and 22 deletions
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2
src/learning_gem5/part2/SimpleCache.py
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@@ -36,7 +36,7 @@ class SimpleCache(ClockedObject):
# Vector port example. Both the instruction and data ports connect to this
# port which is automatically split out into two ports.
cpu_side = VectorSlavePort("CPU side port, receives requests")
mem_side = MasterPort("Memory side port, sends requests")
mem_side = RequestPort("Memory side port, sends requests")
latency = Param.Cycles(1, "Cycles taken on a hit or to resolve a miss")

6
src/learning_gem5/part2/SimpleMemobj.py
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@@ -32,6 +32,6 @@ class SimpleMemobj(SimObject):
type = 'SimpleMemobj'
cxx_header = "learning_gem5/part2/simple_memobj.hh"
inst_port = SlavePort("CPU side port, receives requests")
data_port = SlavePort("CPU side port, receives requests")
mem_side = MasterPort("Memory side port, sends requests")
inst_port = ResponsePort("CPU side port, receives requests")
data_port = ResponsePort("CPU side port, receives requests")
mem_side = RequestPort("Memory side port, sends requests")

8
src/learning_gem5/part2/simple_cache.hh
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@@ -51,7 +51,7 @@ class SimpleCache : public ClockedObject
* Port on the CPU-side that receives requests.
* Mostly just forwards requests to the cache (owner)
*/
class CPUSidePort : public SlavePort
class CPUSidePort : public ResponsePort
{
private:
/// Since this is a vector port, need to know what number this one is
@@ -71,7 +71,7 @@ class SimpleCache : public ClockedObject
* Constructor. Just calls the superclass constructor.
*/
CPUSidePort(const std::string& name, int id, SimpleCache *owner) :
SlavePort(name, owner), id(id), owner(owner), needRetry(false),
ResponsePort(name, owner), id(id), owner(owner), needRetry(false),
blockedPacket(nullptr)
{ }
@@ -137,7 +137,7 @@ class SimpleCache : public ClockedObject
* Port on the memory-side that receives responses.
* Mostly just forwards requests to the cache (owner)
*/
class MemSidePort : public MasterPort
class MemSidePort : public RequestPort
{
private:
/// The object that owns this object (SimpleCache)
@@ -151,7 +151,7 @@ class SimpleCache : public ClockedObject
* Constructor. Just calls the superclass constructor.
*/
MemSidePort(const std::string& name, SimpleCache *owner) :
MasterPort(name, owner), owner(owner), blockedPacket(nullptr)
RequestPort(name, owner), owner(owner), blockedPacket(nullptr)
{ }
/**

28
src/learning_gem5/part2/simple_memobj.hh
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@@ -48,7 +48,7 @@ class SimpleMemobj : public SimObject
* Mostly just forwards requests to the owner.
* Part of a vector of ports. One for each CPU port (e.g., data, inst)
*/
class CPUSidePort : public SlavePort
class CPUSidePort : public ResponsePort
{
private:
/// The object that owns this object (SimpleMemobj)
@@ -65,7 +65,7 @@ class SimpleMemobj : public SimObject
* Constructor. Just calls the superclass constructor.
*/
CPUSidePort(const std::string& name, SimpleMemobj *owner) :
SlavePort(name, owner), owner(owner), needRetry(false),
ResponsePort(name, owner), owner(owner), needRetry(false),
blockedPacket(nullptr)
{ }
@@ -79,7 +79,7 @@ class SimpleMemobj : public SimObject
/**
* Get a list of the non-overlapping address ranges the owner is
* responsible for. All slave ports must override this function
* responsible for. All response ports must override this function
* and return a populated list with at least one item.
*
* @return a list of ranges responded to
@@ -94,14 +94,14 @@ class SimpleMemobj : public SimObject
protected:
/**
* Receive an atomic request packet from the master port.
* Receive an atomic request packet from the request port.
* No need to implement in this simple memobj.
*/
Tick recvAtomic(PacketPtr pkt) override
{ panic("recvAtomic unimpl."); }
/**
* Receive a functional request packet from the master port.
* Receive a functional request packet from the request port.
* Performs a "debug" access updating/reading the data in place.
*
* @param packet the requestor sent.
@@ -109,7 +109,7 @@ class SimpleMemobj : public SimObject
void recvFunctional(PacketPtr pkt) override;
/**
* Receive a timing request from the master port.
* Receive a timing request from the request port.
*
* @param the packet that the requestor sent
* @return whether this object can consume the packet. If false, we
@@ -119,8 +119,8 @@ class SimpleMemobj : public SimObject
bool recvTimingReq(PacketPtr pkt) override;
/**
* Called by the master port if sendTimingResp was called on this
* slave port (causing recvTimingResp to be called on the master
* Called by the request port if sendTimingResp was called on this
* response port (causing recvTimingResp to be called on the request
* port) and was unsuccesful.
*/
void recvRespRetry() override;
@@ -130,7 +130,7 @@ class SimpleMemobj : public SimObject
* Port on the memory-side that receives responses.
* Mostly just forwards requests to the owner
*/
class MemSidePort : public MasterPort
class MemSidePort : public RequestPort
{
private:
/// The object that owns this object (SimpleMemobj)
@@ -144,7 +144,7 @@ class SimpleMemobj : public SimObject
* Constructor. Just calls the superclass constructor.
*/
MemSidePort(const std::string& name, SimpleMemobj *owner) :
MasterPort(name, owner), owner(owner), blockedPacket(nullptr)
RequestPort(name, owner), owner(owner), blockedPacket(nullptr)
{ }
/**
@@ -157,19 +157,19 @@ class SimpleMemobj : public SimObject
protected:
/**
* Receive a timing response from the slave port.
* Receive a timing response from the response port.
*/
bool recvTimingResp(PacketPtr pkt) override;
/**
* Called by the slave port if sendTimingReq was called on this
* master port (causing recvTimingReq to be called on the slave
* Called by the response port if sendTimingReq was called on this
* request port (causing recvTimingReq to be called on the responder
* port) and was unsuccesful.
*/
void recvReqRetry() override;
/**
* Called to receive an address range change from the peer slave
* Called to receive an address range change from the peer responder
* port. The default implementation ignores the change and does
* nothing. Override this function in a derived class if the owner
* needs to be aware of the address ranges, e.g. in an