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fastmodel: Plumb the ITB and DTB through the IRIS thread context.

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These might be necessary to, for instance, translate virtual addresses.
A custom TLB which uses the IRIS API will be written which can be
substituted in for the normal ARM TLB.

Change-Id: Ic44822db6692ca3a4ca13875b2260b08547a24da
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22116
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Gabe Black
2019-10-15 18:19:18 -07:00
parent 2c3c7df5fc
commit bff1d59511
5 changed files with 13 additions and 8 deletions
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4
src/arch/arm/fastmodel/iris/arm/thread_context.cc
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@@ -36,10 +36,10 @@ namespace Iris
{
ArmThreadContext::ArmThreadContext(
::BaseCPU *cpu, int id, System *system,
::BaseCPU *cpu, int id, System *system, ::BaseTLB *dtb, ::BaseTLB *itb,
iris::IrisConnectionInterface *iris_if,
const std::string &iris_path) :
ThreadContext(cpu, id, system, iris_if, iris_path),
ThreadContext(cpu, id, system, dtb, itb, iris_if, iris_path),
pcRscId(iris::IRIS_UINT64_MAX)
{}

1
src/arch/arm/fastmodel/iris/arm/thread_context.hh
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@@ -46,6 +46,7 @@ class ArmThreadContext : public Iris::ThreadContext
public:
ArmThreadContext(::BaseCPU *cpu, int id, System *system,
::BaseTLB *dtb, ::BaseTLB *itb,
iris::IrisConnectionInterface *iris_if,
const std::string &iris_path);

3
src/arch/arm/fastmodel/iris/cpu.hh
View File

@@ -135,7 +135,8 @@ class CPU : public Iris::BaseCPU
int thread_id = 0;
for (const std::string &sub_path: params->thread_paths) {
std::string path = parent_path + "." + sub_path;
auto *tc = new TC(this, thread_id++, sys, iris_if, path);
auto *tc = new TC(this, thread_id++, sys,
params->dtb, params->itb,iris_if, path);
threadContexts.push_back(tc);
}
}

6
src/arch/arm/fastmodel/iris/thread_context.cc
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@@ -159,10 +159,10 @@ ThreadContext::simulationTimeEvent(
}
ThreadContext::ThreadContext(
BaseCPU *cpu, int id, System *system,
BaseCPU *cpu, int id, System *system, ::BaseTLB *dtb, ::BaseTLB *itb,
iris::IrisConnectionInterface *iris_if, const std::string &iris_path) :
_cpu(cpu), _threadId(id), _system(system), _irisPath(iris_path),
_instId(iris::IRIS_UINT64_MAX), _status(Active),
_cpu(cpu), _threadId(id), _system(system), _dtb(dtb), _itb(itb),
_irisPath(iris_path), _instId(iris::IRIS_UINT64_MAX), _status(Active),
comInstEventQueue("instruction-based event queue"),
client(iris_if, "client." + iris_path)
{

7
src/arch/arm/fastmodel/iris/thread_context.hh
View File

@@ -55,6 +55,8 @@ class ThreadContext : public ::ThreadContext
int _threadId;
ContextID _contextId;
System *_system;
::BaseTLB *_dtb;
::BaseTLB *_itb;
std::string _irisPath;
iris::InstanceId _instId;
@@ -101,6 +103,7 @@ class ThreadContext : public ::ThreadContext
public:
ThreadContext(::BaseCPU *cpu, int id, System *system,
::BaseTLB *dtb, ::BaseTLB *itb,
iris::IrisConnectionInterface *iris_if,
const std::string &iris_path);
virtual ~ThreadContext();
@@ -125,12 +128,12 @@ class ThreadContext : public ::ThreadContext
BaseTLB *
getITBPtr() override
{
panic("%s not implemented.", __FUNCTION__);
return _itb;
}
BaseTLB *
getDTBPtr() override
{
panic("%s not implemented.", __FUNCTION__);
return _dtb;
}
CheckerCPU *
getCheckerCpuPtr() override