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This is where I'm at for Linux Ethernet before I head to Mexico.

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base/range.hh:
    andrew thought this might be a bug.
dev/etherpkt.cc:
    don't need std:: since there is a using directive
dev/ns_gige.cc:
    update to new PIO and PCI system
dev/ns_gige.hh:
    update to deal with new PIO and PCI setup
dev/ns_gige_reg.h:
    Add some new #defines that I ended up needing
dev/pcidev.cc:
    some changes to the debugging printfs of pci device

--HG--
extra : convert_revision : 955ba8e8e1c418cfe1c6549dc3451ea091541556
This commit is contained in:
Lisa Hsu
2004-04-21 18:23:41 -04:00
parent f4168a708c
commit bf8de77465
6 changed files with 1355 additions and 926 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
base/range.hh
View File

@@ -225,7 +225,7 @@ inline bool
operator==(const T &pos, const Range<U> &range)
{
assert(range.valid());
return pos >= range.start && pos < range.end;
return pos >= range.start && pos <= range.end;
}
/**

2
dev/etherpkt.cc
View File

@@ -41,7 +41,7 @@ EtherPacket::serialize(ostream &os)
}
void
EtherPacket::unserialize(Checkpoint *cp, const std::string &section)
EtherPacket::unserialize(Checkpoint *cp, const string &section)
{
UNSERIALIZE_SCALAR(length);
data = new uint8_t[length];

1909
dev/ns_gige.cc
View File

File diff suppressed because it is too large Load Diff

343
dev/ns_gige.hh
View File

@@ -34,7 +34,7 @@
#ifndef __NS_GIGE_HH__
#define __NS_GIGE_HH__
#include "dev/dma.hh"
//#include "base/range.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
#include "sim/eventq.hh"
@@ -42,7 +42,8 @@
#include "base/statistics.hh"
#include "dev/pcidev.hh"
#include "dev/tsunami.hh"
#include "dev/pciconfigall.hh"
#include "dev/io_device.hh"
#include "mem/bus/bus.hh"
/** defined by the NS83820 data sheet */
#define MAX_TX_FIFO_SIZE 8192
@@ -51,14 +52,6 @@
/** length of ethernet address in bytes */
#define EADDR_LEN 6
/** Transmit State Machine states */
enum tx_state { txIdle, txDescRefr, txDescRead, txFifoBlock, txFragRead,
txDescWrite };
/** Receive State Machine States */
enum rx_state { rxIdle, rxDescRefr, rxDescRead, rxFifoBlock, rxFragWrite,
rxDescWrite, rxAdvance };
/**
* Ethernet device registers
*/
@@ -95,173 +88,174 @@ struct dp_regs {
uint32_t tanlpar;
uint32_t taner;
uint32_t tesr;
/** for perfect match memory. the linux driver doesn't use any other ROM */
uint8_t perfectMatch[EADDR_LEN];
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
};
/** an enum indicating direction, transmit or receive, used as a param for
some fns */
enum dir_t { tx, rx };
struct dp_rom {
/** for perfect match memory. the linux driver doesn't use any other ROM */
uint8_t perfectMatch[EADDR_LEN];
};
class DmaEngine;
class IntrControl;
class EtherDevInt;
class PhysicalMemory;
class BaseInterface;
class HierParams;
class Bus;
class PciConfigAll;
/**
* NS DP82830 Ethernet device model
*/
class EtherDev : public PciDev, public DmaHolder
class EtherDev : public PciDev
{
public:
/** Transmit State Machine states */
enum TxState
{
txIdle,
txDescRefr,
txDescRead,
txFifoBlock,
txFragRead,
txDescWrite,
txAdvance
};
/** Receive State Machine States */
enum RxState
{
rxIdle,
rxDescRefr,
rxDescRead,
rxFifoBlock,
rxFragWrite,
rxDescWrite,
rxAdvance
};
enum DmaState
{
dmaIdle,
dmaReading,
dmaWriting,
dmaReadWaiting,
dmaWriteWaiting
};
private:
/** pointer to the chipset */
Tsunami *tsunami;
protected:
private:
Addr addr;
Addr mask;
static const Addr size = sizeof(dp_regs);
protected:
typedef std::deque<PacketPtr> pktbuf_t;
typedef pktbuf_t::iterator pktiter_t;
/** device register file */
dp_regs regs;
dp_rom rom;
/*** BASIC STRUCTURES FOR TX/RX ***/
/* Data FIFOs */
typedef std::deque<PacketPtr> pktbuf_t;
typedef pktbuf_t::iterator pktiter_t;
pktbuf_t txFifo;
pktbuf_t rxFifo;
/** for the tx side, to track addrs to write updated cmdsts to */
typedef std::deque<uint32_t> txdpbuf_t; /* ASSUME32 */
txdpbuf_t descAddrFifo;
/** various helper vars */
uint32_t txPacketLen;
uint8_t *txPacketBufPtr;
uint8_t *rxPacketBufPtr;
uint8_t *rxDescBufPtr;
uint32_t fragLen;
uint32_t rxCopied;
uint32_t txXferLen;
uint32_t rxXferLen;
uint32_t txPktXmitted;
bool rxDmaFree;
bool txDmaFree;
PacketPtr txPacket;
PacketPtr rxPacket;
/** DescCaches */
ns_desc txDescCache;
ns_desc rxDescCache;
/* tx State Machine */
tx_state txState;
TxState txState;
/** Current Transmit Descriptor Done */
bool CTDD;
uint32_t txFifoCnt; /* amt of data in the txDataFifo in bytes (logical) */
uint32_t txFifoAvail; /* current amt of free space in txDataFifo in byes */
/** amt of data in the txDataFifo in bytes (logical) */
uint32_t txFifoCnt;
/** current amt of free space in txDataFifo in bytes */
uint32_t txFifoAvail;
/** halt the tx state machine after next packet */
bool txHalt;
bool txPacketFlag; /* when set, indicates not working on a new packet */
Addr txFragPtr; /* ptr to the next byte in the current fragment */
uint32_t txDescCnt; /* count of bytes remaining in the current descriptor */
/** ptr to the next byte in the current fragment */
Addr txFragPtr;
/** count of bytes remaining in the current descriptor */
uint32_t txDescCnt;
DmaState txDmaState;
/** rx State Machine */
rx_state rxState;
bool CRDD; /* Current Receive Descriptor Done */
uint32_t rxPktBytes; /* num of bytes in the current packet being drained
from rxDataFifo */
uint32_t rxFifoCnt; /* number of bytes in the rxFifo */
RxState rxState;
/** Current Receive Descriptor Done */
bool CRDD;
/** num of bytes in the current packet being drained from rxDataFifo */
uint32_t rxPktBytes;
/** number of bytes in the rxFifo */
uint32_t rxFifoCnt;
/** halt the rx state machine after current packet */
bool rxHalt;
bool rxPacketFlag; /* when set, indicates not working on a new packet */
Addr rxFragPtr; /* ptr to the next byte in current fragment */
uint32_t rxDescCnt; /* count of bytes remaining in the current descriptor */
/** ptr to the next byte in current fragment */
Addr rxFragPtr;
/** count of bytes remaining in the current descriptor */
uint32_t rxDescCnt;
DmaState rxDmaState;
bool extstsEnable;
uint32_t maxTxBurst;
uint32_t maxRxBurst;
PhysicalMemory *physmem;
protected:
/**
* Receive dma for descriptors done callback
*/
class RxDescDone : public DmaCallback
{
public:
EtherDev *ethernet;
Tick dmaReadDelay;
Tick dmaWriteDelay;
public:
RxDescDone(EtherDev *e);
std::string name() const;
virtual void process();
};
Tick dmaReadFactor;
Tick dmaWriteFactor;
/**
* Receive dma done callback
*/
class RxDone : public DmaCallback
{
public:
EtherDev *ethernet;
void *rxDmaData;
Addr rxDmaAddr;
int rxDmaLen;
bool doRxDmaRead();
bool doRxDmaWrite();
void rxDmaReadCopy();
void rxDmaWriteCopy();
public:
RxDone(EtherDev *e);
std::string name() const;
virtual void process();
};
void *txDmaData;
Addr txDmaAddr;
int txDmaLen;
bool doTxDmaRead();
bool doTxDmaWrite();
void txDmaReadCopy();
void txDmaWriteCopy();
/**
* Transmit dma for descriptors done callback
*/
class TxDescDone : public DmaCallback
{
public:
EtherDev *ethernet;
void rxDmaReadDone();
friend class EventWrapper<EtherDev, &EtherDev::rxDmaReadDone>;
EventWrapper<EtherDev, &EtherDev::rxDmaReadDone> rxDmaReadEvent;
public:
TxDescDone(EtherDev *e);
std::string name() const;
virtual void process();
};
void rxDmaWriteDone();
friend class EventWrapper<EtherDev, &EtherDev::rxDmaWriteDone>;
EventWrapper<EtherDev, &EtherDev::rxDmaWriteDone> rxDmaWriteEvent;
/*
* Transmit dma done callback
*/
class TxDone : public DmaCallback
{
public:
EtherDev *ethernet;
PacketPtr packet;
void txDmaReadDone();
friend class EventWrapper<EtherDev, &EtherDev::txDmaReadDone>;
EventWrapper<EtherDev, &EtherDev::txDmaReadDone> txDmaReadEvent;
public:
TxDone(EtherDev *e);
std::string name() const;
virtual void process();
};
void txDmaWriteDone();
friend class EventWrapper<EtherDev, &EtherDev::txDmaWriteDone>;
EventWrapper<EtherDev, &EtherDev::txDmaWriteDone> txDmaWriteEvent;
friend class TxDescDone;
friend class TxDone;
friend class RxDescDone;
friend class RxDone;
bool dmaDescFree;
bool dmaDataFree;
RxDescDone rxDescDoneCB;
RxDone rxDoneCB;
TxDescDone txDescDoneCB;
TxDone txDoneCB;
DmaEngine *dma;
DmaRequest readRequest;
DmaRequest writeRequest;
DmaRequest readDescRequest;
DmaRequest writeDescRequest;
PacketPtr rxPacket;
DmaPhys readPhys;
DmaPhys writePhys;
DmaPhys readDescPhys;
DmaPhys writeDescPhys;
EtherDevInt *interface;
protected:
IntrControl *intctrl;
Tick txDelay;
Tick rxDelay;
@@ -269,6 +263,7 @@ class EtherDev : public PciDev, public DmaHolder
void rxReset();
void regsReset() {
memset(&regs, 0, sizeof(regs));
regs.config = 0x80000000;
regs.mear = 0x12;
regs.isr = 0x00608000;
regs.txcfg = 0x120;
@@ -279,44 +274,30 @@ class EtherDev : public PciDev, public DmaHolder
regs.tesr = 0xc000;
}
void txKick();
void rxKick();
Tick rxKickTick;
typedef EventWrapper<EtherDev, &EtherDev::rxKick> RxKickEvent;
friend class RxKickEvent;
/*
void txKick();
Tick txKickTick;
typedef EventWrapper<EtherDev, &EtherDev::txKick> TxKickEvent;
friend class TxKickEvent;
/**
* Retransmit event
*/
class TxEvent : public Event
{
protected:
EtherDev *dev;
public:
TxEvent(EtherDev *_dev)
: Event(&mainEventQueue), dev(_dev) {}
void process() { dev->transmit(); }
virtual const char *description() { return "retransmit"; }
};
void transmit();
typedef EventWrapper<EtherDev, &EtherDev::transmit> TxEvent;
friend class TxEvent;
TxEvent txEvent;
void transmit();
void txDescDone();
void rxDescDone();
void txDone(PacketPtr packet);
void rxDone();
void txDump() const;
void rxDump() const;
void devIntrPost(uint32_t interrupts);
void devIntrClear(uint32_t interrupts);
void devIntrChangeMask();
bool cpuPendingIntr;
void cpuIntrPost();
void cpuIntrClear();
/**
* receive address filter
*/
bool rxFilterEnable;
bool rxFilter(PacketPtr packet);
bool acceptBroadcast;
@@ -325,26 +306,53 @@ class EtherDev : public PciDev, public DmaHolder
bool acceptPerfect;
bool acceptArp;
PhysicalMemory *physmem;
/**
* Interrupt management
*/
IntrControl *intctrl;
void devIntrPost(uint32_t interrupts);
void devIntrClear(uint32_t interrupts);
void devIntrChangeMask();
Tick intrDelay;
Tick intrTick;
bool cpuPendingIntr;
void cpuIntrPost(Tick when);
void cpuInterrupt();
void cpuIntrClear();
typedef EventWrapper<EtherDev, &EtherDev::cpuInterrupt> IntrEvent;
friend class IntrEvent;
IntrEvent *intrEvent;
/**
* Hardware checksum support
*/
bool udpChecksum(PacketPtr packet, bool gen);
bool tcpChecksum(PacketPtr packet, bool gen);
bool ipChecksum(PacketPtr packet, bool gen);
uint16_t checksumCalc(uint16_t *pseudo, uint16_t *buf, uint32_t len);
EtherDevInt *interface;
public:
EtherDev(const std::string &name, DmaEngine *de, bool use_interface,
IntrControl *i, MemoryController *mmu, PhysicalMemory *pmem,
PCIConfigAll *cf, PciConfigData *cd, Tsunami *t, uint32_t bus,
uint32_t dev, uint32_t func, bool rx_filter, const int eaddr[6],
Tick tx_delay, Tick rx_delay, Addr addr, Addr mask);
EtherDev(const std::string &name, IntrControl *i, Tick intr_delay,
PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay,
MemoryController *mmu, HierParams *hier, Bus *header_bus,
Bus *payload_bus, Tick pio_latency, bool dma_desc_free,
bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
uint32_t func, bool rx_filter, const int eaddr[6], Addr addr);
~EtherDev();
virtual void WriteConfig(int offset, int size, uint32_t data);
virtual void ReadConfig(int offset, int size, uint8_t *data);
Fault read(MemReqPtr req, uint8_t *data);
Fault write(MemReqPtr req, const uint8_t *data);
virtual Fault read(MemReqPtr &req, uint8_t *data);
virtual Fault write(MemReqPtr &req, const uint8_t *data);
bool cpuIntrPending() const;
void cpuIntrAck() { cpuIntrClear(); }
@@ -357,15 +365,6 @@ class EtherDev : public PciDev, public DmaHolder
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
virtual DmaRequest *find_dmareq(uint32_t &id) {
if (id == 0)
return(&readRequest);
else if (id == 1)
return(&writeRequest);
else
return(NULL);
}
public:
void regStats();
@@ -379,9 +378,11 @@ class EtherDev : public PciDev, public DmaHolder
Statistics::Formula txPacketRate;
Statistics::Formula rxPacketRate;
void readOneDesc(dir_t dir, uint32_t len = sizeof(ns_desc));
void readOneFrag();
void writeOneFrag();
private:
Tick pioLatency;
public:
Tick cacheAccess(MemReqPtr &req);
};
/*

11
dev/ns_gige_reg.h
View File

@@ -109,6 +109,8 @@
#define BRDR 0x54
#define SRR 0x58
#define MIBC 0x5c
#define MIB_START 0x60
#define MIB_END 0x88
#define VRCR 0xbc
#define VTCR 0xc0
#define VDR 0xc4
@@ -182,6 +184,7 @@
#define PTSCR_RBIST_DONE 0x00000200
#define PTSCR_RBIST_EN 0x00000400
#define PTSCR_RBIST_RST 0x00002000
#define PTSCR_RBIST_RDONLY 0x000003f9
/* interrupt status register */
#define ISR_RESERVE 0x80000000
@@ -232,6 +235,7 @@
#define TXCFG_MXDMA32 0x00300000
#define TXCFG_MXDMA16 0x00200000
#define TXCFG_MXDMA8 0x00100000
#define TXCFG_MXDMA 0x00700000
#define TXCFG_FLTH_MASK 0x0000ff00
#define TXCFG_DRTH_MASK 0x000000ff
@@ -253,6 +257,7 @@
#define RXCFG_ALP 0x08000000
#define RXCFG_AIRL 0x04000000
#define RXCFG_MXDMA512 0x00700000
#define RXCFG_MXDMA 0x00700000
#define RXCFG_DRTH 0x0000003e
#define RXCFG_DRTH0 0x00000002
@@ -339,12 +344,6 @@ struct ns_desc {
uint32_t extsts; /* extended status field for VLAN and IP info */
};
/* ASSUME32 in bytes, how big the desc fields are */
#define LINK_LEN 4
#define BUFPTR_LEN 4
#define CMDSTS_LEN 4
#define EXTSTS_LEN 4
/* cmdsts flags for descriptors */
#define CMDSTS_OWN 0x80000000
#define CMDSTS_MORE 0x40000000

14
dev/pcidev.cc
View File

@@ -77,24 +77,24 @@ PciDev::ReadConfig(int offset, int size, uint8_t *data)
case sizeof(uint32_t):
memcpy((uint32_t*)data, config.data + offset, sizeof(uint32_t));
DPRINTF(PCIDEV,
"read device: %#x function: %#x register: %#x data: %#x\n",
deviceNum, functionNum, offset,
"read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
deviceNum, functionNum, offset, size,
*(uint32_t*)(config.data + offset));
break;
case sizeof(uint16_t):
memcpy((uint16_t*)data, config.data + offset, sizeof(uint16_t));
DPRINTF(PCIDEV,
"read device: %#x function: %#x register: %#x data: %#x\n",
deviceNum, functionNum, offset,
"read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
deviceNum, functionNum, offset, size,
*(uint16_t*)(config.data + offset));
break;
case sizeof(uint8_t):
memcpy((uint8_t*)data, config.data + offset, sizeof(uint8_t));
DPRINTF(PCIDEV,
"read device: %#x function: %#x register: %#x data: %#x\n",
deviceNum, functionNum, offset,
"read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
deviceNum, functionNum, offset, size,
(uint16_t)(*(uint8_t*)(config.data + offset)));
break;
@@ -116,7 +116,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
word_value = data;
DPRINTF(PCIDEV,
"write device: %#x function: %#x reg: %#x size: %#x data: %#x\n",
"write device: %#x function: %#x reg: %#x size: %d data: %#x\n",
deviceNum, functionNum, offset, size, word_value);
barnum = (offset - PCI0_BASE_ADDR0) >> 2;