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cpu-o3: print VecPredReg not VecReg

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Fix a DPRINTF to print the VecPredReg instead of the VecReg.

Change-Id: Iaba255b6b9a98826ddcd67eb83b4169e1bf5056e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64342
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Sascha Bischoff
2022-08-31 10:37:02 +01:00
committed by Giacomo Travaglini
parent 41b5276c1c
commit befa5baa78
1 changed files with 1 additions and 1 deletions
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2
src/cpu/o3/regfile.hh
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@@ -299,7 +299,7 @@ class PhysRegFile
break;
case VecPredRegClass:
DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
idx, vectorRegFile.regClass.valString(val));
idx, vecPredRegFile.regClass.valString(val));
vecPredRegFile.set(idx, val);
break;
case CCRegClass: