From befa5baa78bce145e47ae4ef6a9e1b4da6e46978 Mon Sep 17 00:00:00 2001
From: Sascha Bischoff <sascha.bischoff@arm.com>
Date: Wed, 31 Aug 2022 10:37:02 +0100
Subject: [PATCH] cpu-o3: print VecPredReg not VecReg

Fix a DPRINTF to print the VecPredReg instead of the VecReg.

Change-Id: Iaba255b6b9a98826ddcd67eb83b4169e1bf5056e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64342
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/cpu/o3/regfile.hh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 0130c55625..4fea589ad7 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -299,7 +299,7 @@ class PhysRegFile
             break;
           case VecPredRegClass:
             DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
-                    idx, vectorRegFile.regClass.valString(val));
+                    idx, vecPredRegFile.regClass.valString(val));
             vecPredRegFile.set(idx, val);
             break;
           case CCRegClass: