arch-arm: Reduce boilerplate when extracting SelfDebug from tc

Change-Id: I1746400617be64ac9c2f3194442734e178342909
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31354
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/faults.cc

@@ -723,8 +723,7 @@ ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst)
 bool
 ArmFault::vectorCatch(ThreadContext *tc, const StaticInstPtr &inst)
 {
-    auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
-    SelfDebug * sd = isa->getSelfDebug();
+    SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc);
     VectorCatch* vc = sd->getVectorCatch(tc);
     if (!vc->isVCMatch()) {
         Fault fault = sd->testVectorCatch(tc, 0x0, this);

src/arch/arm/insts/pseudo.cc

@@ -201,8 +201,11 @@ DebugStep::execute(ExecContext *xc, Trace::InstRecord *traceData) const
     PCState pc_state(xc->pcState());
     pc_state.debugStep(false);
     xc->pcState(pc_state);
-    auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
-    bool ldx = isa->getSelfDebug()->getSstep()->getLdx();
+
+    SelfDebug *sd = ArmISA::ISA::getSelfDebug(xc->tcBase());
+
+    bool ldx = sd->getSstep()->getLdx();
+
     return std::make_shared<SoftwareStepFault>(machInst, ldx,
                                                pc_state.stepped());
 

src/arch/arm/insts/static_inst.cc

@@ -1192,8 +1192,8 @@ ArmStaticInst::getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const
         new_cpsr.daif = spsr.daif;
     }
 
-    auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
-    SoftwareStep * ss = (isa->getSelfDebug())->getSstep();
+    SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc);
+    SoftwareStep *ss = sd->getSstep();
     new_cpsr.ss = ss->debugExceptionReturnSS(tc, spsr, dest, new_cpsr.width);
 
     return new_cpsr;

src/arch/arm/insts/static_inst.hh

@@ -203,8 +203,7 @@ class ArmStaticInst : public StaticInst
     static void
     activateBreakpoint(ThreadContext *tc)
     {
-        auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
-        SelfDebug * sd = isa->getSelfDebug();
+        SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc);
         sd->activateDebug();
     }
 

src/arch/arm/isa.hh

@@ -466,10 +466,19 @@ namespace ArmISA
         void initID64(const ArmISAParams *p);
 
       public:
-        SelfDebug * getSelfDebug()
+        SelfDebug*
+        getSelfDebug() const
         {
             return selfDebug;
         }
+
+        static SelfDebug*
+        getSelfDebug(ThreadContext *tc)
+        {
+            auto *arm_isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
+            return arm_isa->getSelfDebug();
+        }
+
         RegVal readMiscRegNoEffect(int misc_reg) const;
         RegVal readMiscReg(int misc_reg);
         void setMiscRegNoEffect(int misc_reg, RegVal val);

src/arch/arm/isa/insts/ldr.isa

@@ -211,9 +211,8 @@ let {{
 
             if self.flavor in ('exclusive', 'acex'):
                 accCode += '''
-           auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
-           SelfDebug * sd = isa->getSelfDebug();
-           sd->getSstep()->setLdx();
+                SelfDebug *sd = ArmISA::ISA::getSelfDebug(xc->tcBase());
+                sd->getSstep()->setLdx();
               '''
 
             self.codeBlobs["memacc_code"] = accCode
@@ -293,9 +292,8 @@ let {{
                 '''
             if self.flavor in ('exclusive', 'acex'):
                 accCode += '''
-             auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
-             SelfDebug * sd = isa->getSelfDebug();
-             sd->getSstep()->setLdx();
+                SelfDebug *sd = ArmISA::ISA::getSelfDebug(xc->tcBase());
+                sd->getSstep()->setLdx();
              '''
 
             self.codeBlobs["memacc_code"] = accCode

src/arch/arm/isa/insts/ldr64.isa

@@ -243,9 +243,8 @@ let {{
             accCode = accCode % buildMemSuffix(self.sign, self.size)
             if self.flavor in ('exclusive', 'acex'):
                 accCode += '''
-             auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
-             SelfDebug * sd = isa->getSelfDebug();
-             sd->getSstep()->setLdx();
+                SelfDebug *sd = ArmISA::ISA::getSelfDebug(xc->tcBase());
+                sd->getSstep()->setLdx();
              '''
             self.codeBlobs["memacc_code"] = accCode
             if accEpilogCode:
@@ -344,9 +343,8 @@ let {{
                         '''
             if self.flavor in ('exp', 'acexp'):
                 accCode += '''
-             auto *isa = static_cast<ArmISA::ISA *>(xc->tcBase()->getIsaPtr());
-             SelfDebug * sd = isa->getSelfDebug();
-             sd->getSstep()->setLdx();
+                SelfDebug *sd = ArmISA::ISA::getSelfDebug(xc->tcBase());
+                sd->getSstep()->setLdx();
              '''
             self.codeBlobs["memacc_code"] = accCode
             if accEpilogCode:

src/arch/arm/tlb.cc

@@ -1234,8 +1234,7 @@ TLB::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode,
 
     //Check for Debug Exceptions
     if (fault == NoFault) {
-        auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
-        SelfDebug *sd = isa->getSelfDebug();
+        SelfDebug *sd = ArmISA::ISA::getSelfDebug(tc);
 
         fault = sd->testDebug(tc, req, mode);
     }