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mem: Schedule time for DRAM event taking tRAS into account

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This patch changes the time the controller is woken up to take the
next scheduling decisions. tRAS is now handled in estimateLatency and
doDRAMAccess and we do not need to worry about it at scheduling
time. The earliest we need to wake up is to do a pre-charge, row
access and column access before the bus becomes free for use.
This commit is contained in:
Ani Udipi
2013-11-01 11:56:17 -04:00
parent d4cf009b95
commit be62a142cf
1 changed files with 4 additions and 5 deletions
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9
src/mem/simple_dram.cc
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@@ -1135,12 +1135,11 @@ SimpleDRAM::doDRAMAccess(DRAMPacket* dram_pkt)
// The absolute soonest you have to start thinking about the
// next request is the longest access time that can occur before
// busBusyUntil. Assuming you need to meet tRAS, then precharge,
// open a new row, and access, it is ~4*tRCD.
// busBusyUntil. Assuming you need to precharge,
// open a new row, and access, it is tRP + tRCD + tCL
Tick newTime = (busBusyUntil > 4 * tRCD) ?
std::max(busBusyUntil - 4 * tRCD, curTick()) :
Tick newTime = (busBusyUntil > tRP + tRCD + tCL ) ?
std::max(busBusyUntil - (tRP + tRCD + tCL) , curTick()) :
curTick();
if (!nextReqEvent.scheduled() && !stopReads){