derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ARM: Decode the SADD8 and SADD16 instructions.

Browse Source
This commit is contained in:
Gabe Black
2010-06-02 12:58:06 -05:00
parent 87975aa691
commit bcf0454864
1 changed files with 23 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

54
src/arch/arm/isa/formats/data.isa
View File

@@ -234,7 +234,7 @@ def format ArmParallelAddSubtract() {{
case 0x1:
switch (op2) {
case 0x0:
return new WarnUnimplemented("sadd16", machInst);
return new Sadd16RegCc(machInst, rd, rn, rm, 0, LSL);
case 0x1:
return new WarnUnimplemented("sasx", machInst);
case 0x2:
@@ -242,7 +242,7 @@ def format ArmParallelAddSubtract() {{
case 0x3:
return new WarnUnimplemented("ssub16", machInst);
case 0x4:
return new WarnUnimplemented("sadd8", machInst);
return new Sadd8RegCc(machInst, rd, rn, rm, 0, LSL);
case 0x7:
return new WarnUnimplemented("ssub8", machInst);
}
@@ -542,11 +542,16 @@ def format Thumb32DataProcReg() {{
if (bits(op2, 2) == 0x0) {
const uint32_t op1 = bits(machInst, 22, 20);
const uint32_t op2 = bits(machInst, 5, 4);
const IntRegIndex rd =
(IntRegIndex)(uint32_t)bits(machInst, 11, 8);
const IntRegIndex rm =
(IntRegIndex)(uint32_t)bits(machInst, 3, 0);
switch (op2) {
case 0x0:
switch (op1) {
case 0x1:
return new WarnUnimplemented("sadd16", machInst);
return new Sadd16RegCc(machInst, rd,
rn, rm, 0, LSL);
case 0x2:
return new WarnUnimplemented("sasx", machInst);
case 0x6:
@@ -554,39 +559,26 @@ def format Thumb32DataProcReg() {{
case 0x5:
return new WarnUnimplemented("ssub16", machInst);
case 0x0:
return new WarnUnimplemented("sadd8", machInst);
return new Sadd8RegCc(machInst, rd,
rn, rm, 0, LSL);
case 0x4:
return new WarnUnimplemented("ssub8", machInst);
}
break;
case 0x1:
{
IntRegIndex rn =
(IntRegIndex)(uint32_t)bits(machInst, 19, 16);
IntRegIndex rd =
(IntRegIndex)(uint32_t)bits(machInst, 11, 8);
IntRegIndex rm =
(IntRegIndex)(uint32_t)bits(machInst, 3, 0);
switch (op1) {
case 0x1:
return new Qadd16Reg(machInst, rd,
rn, rm, 0, LSL);
case 0x2:
return new QasxReg(machInst, rd,
rn, rm, 0, LSL);
case 0x6:
return new QsaxReg(machInst, rd,
rn, rm, 0, LSL);
case 0x5:
return new Qsub16Reg(machInst, rd,
rn, rm, 0, LSL);
case 0x0:
return new Qsub8Reg(machInst, rd,
rn, rm, 0, LSL);
case 0x4:
return new Qsub8Reg(machInst, rd,
rn, rm, 0, LSL);
}
switch (op1) {
case 0x1:
return new Qadd16Reg(machInst, rd, rn, rm, 0, LSL);
case 0x2:
return new QasxReg(machInst, rd, rn, rm, 0, LSL);
case 0x6:
return new QsaxReg(machInst, rd, rn, rm, 0, LSL);
case 0x5:
return new Qsub16Reg(machInst, rd, rn, rm, 0, LSL);
case 0x0:
return new Qadd8Reg(machInst, rd, rn, rm, 0, LSL);
case 0x4:
return new Qsub8Reg(machInst, rd, rn, rm, 0, LSL);
}
break;
case 0x2: