cpu-o3: fix dispatch assert triggering on debug mode

On configs with renameWidth > dispatchWidth, on receiving
renameWidth number of only squashed instructions:
the dispatch stage will not be able to treat all instructions.
Some squashed instructions will then remain in the 'inst' buffer
after the dispatch stage.

'validInstsFromRename' function don't take into account squashed
instructions, thus the remaining squashed instructions are
not moved to the skid buffer.

The cycle after, the assert in sortInsts will trigger(on debug mode)
because the 'inst' buffer is not empty.

Change-Id: I1a1ed5a7f040041363bd1b2c7bf10c85eb7febaf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46600
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/cpu/o3/iew.cc

@@ -590,19 +590,6 @@ IEW::instToCommit(const DynInstPtr& inst)
     (*iewQueue)[wbCycle].size++;
 }
 
-unsigned
-IEW::validInstsFromRename()
-{
-    unsigned inst_count = 0;
-
-    for (int i=0; i<fromRename->size; i++) {
-        if (!fromRename->insts[i]->isSquashed())
-            inst_count++;
-    }
-
-    return inst_count;
-}
-
 void
 IEW::skidInsert(ThreadID tid)
 {
@@ -875,7 +862,7 @@ IEW::dispatch(ThreadID tid)
 
         ++iewStats.unblockCycles;
 
-        if (validInstsFromRename()) {
+        if (fromRename->size != 0) {
             // Add the current inputs to the skid buffer so they can be
             // reprocessed when this stage unblocks.
             skidInsert(tid);

src/cpu/o3/iew.hh

@@ -271,11 +271,6 @@ class IEW
      */
     void writebackInsts();
 
-    /** Returns the number of valid, non-squashed instructions coming from
-     * rename to dispatch.
-     */
-    unsigned validInstsFromRename();
-
     /** Checks if any of the stall conditions are currently true. */
     bool checkStall(ThreadID tid);