dev, arm: remove the RealViewEB platform
This is an old platform, and we haven't had official Linux kernel configs for it in a while, so we've decided to deprecate it. Furthermore, trying to use it fails with: object 'RealViewEB' has no attribute 'pci_host' and the last commit in the class happened two years ago, which indicates that no one has been using it. Change-Id: Icc674b00b152eb3246e05141dbaf2624cc720f21 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/12471 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Ciro Santilli
@@ -211,14 +211,12 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
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assert machine_type
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default_dtbs = {
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"RealViewEB": None,
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"RealViewPBX": None,
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"VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb" % num_cpus,
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"VExpress_EMM64": "vexpress.aarch64.20140821.dtb",
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}
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default_kernels = {
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"RealViewEB": "vmlinux.arm.smp.fb.2.6.38.8",
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"RealViewPBX": "vmlinux.arm.smp.fb.2.6.38.8",
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"VExpress_EMM": "vmlinux.aarch32.ll_20131205.0-gem5",
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"VExpress_EMM64": "vmlinux.aarch64.20140821",
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@@ -52,7 +52,6 @@ _platform_classes = {}
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# Platform aliases. The platforms listed here might not be compiled,
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# we make sure they exist before we add them to the platform list.
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_platform_aliases_all = [
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("RealView_EB", "RealViewEB"),
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("RealView_PBX", "RealViewPBX"),
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("VExpress_GEM5", "VExpress_GEM5_V1"),
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]
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@@ -45,7 +45,6 @@ from ArmSemihosting import ArmSemihosting
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class ArmMachineType(Enum):
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map = {
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'RealViewEB' : 827,
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'RealViewPBX' : 1901,
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'VExpress_EMM' : 2272,
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'VExpress_EMM64' : 2272,
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@@ -741,120 +741,6 @@ class RealViewPBX(RealView):
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self.flash_fake.clk_domain = clkdomain
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self.energy_ctrl.clk_domain = clkdomain
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# Reference for memory map and interrupt number
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# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
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# Chapter 4: Programmer's Reference
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class RealViewEB(RealView):
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uart = Pl011(pio_addr=0x10009000, int_num=44)
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realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500)
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mcc = VExpressMCC()
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dcc = CoreTile2A15DCC()
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gic = GicV2(dist_addr=0x10041000, cpu_addr=0x10040000)
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timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
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timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
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clcd = Pl111(pio_addr=0x10020000, int_num=23)
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kmi0 = Pl050(pio_addr=0x10006000, int_num=20, ps2=PS2Keyboard())
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kmi1 = Pl050(pio_addr=0x10007000, int_num=21, ps2=PS2TouchKit())
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l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
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flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
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fake_mem=True)
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dmac_fake = AmbaFake(pio_addr=0x10030000)
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uart1_fake = AmbaFake(pio_addr=0x1000a000)
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uart2_fake = AmbaFake(pio_addr=0x1000b000)
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uart3_fake = AmbaFake(pio_addr=0x1000c000)
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smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
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smc_fake = AmbaFake(pio_addr=0x100e1000)
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sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
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watchdog_fake = AmbaFake(pio_addr=0x10010000)
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gpio0_fake = AmbaFake(pio_addr=0x10013000)
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gpio1_fake = AmbaFake(pio_addr=0x10014000)
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gpio2_fake = AmbaFake(pio_addr=0x10015000)
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ssp_fake = AmbaFake(pio_addr=0x1000d000)
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sci_fake = AmbaFake(pio_addr=0x1000e000)
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aaci_fake = AmbaFake(pio_addr=0x10004000)
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mmc_fake = AmbaFake(pio_addr=0x10005000)
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rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
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energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
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# Attach I/O devices that are on chip and also set the appropriate
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# ranges for the bridge
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def attachOnChipIO(self, bus, bridge):
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self.gic.pio = bus.master
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self.l2x0_fake.pio = bus.master
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# Bridge ranges based on excluding what is part of on-chip I/O
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# (gic, l2x0)
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bridge.ranges = [AddrRange(self.realview_io.pio_addr,
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self.gic.cpu_addr - 1),
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AddrRange(self.flash_fake.pio_addr, Addr.max)]
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# Set the clock domain for IO objects that are considered
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# to be "close" to the cores.
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def onChipIOClkDomain(self, clkdomain):
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self.gic.clk_domain = clkdomain
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self.l2x0_fake.clk_domain = clkdomain
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# Attach I/O devices to specified bus object. Can't do this
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# earlier, since the bus object itself is typically defined at the
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# System level.
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def attachIO(self, bus):
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self.uart.pio = bus.master
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self.realview_io.pio = bus.master
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self.pci_host.pio = bus.master
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self.timer0.pio = bus.master
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self.timer1.pio = bus.master
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self.clcd.pio = bus.master
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self.clcd.dma = bus.slave
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self.kmi0.pio = bus.master
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self.kmi1.pio = bus.master
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self.dmac_fake.pio = bus.master
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self.uart1_fake.pio = bus.master
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self.uart2_fake.pio = bus.master
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self.uart3_fake.pio = bus.master
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self.smc_fake.pio = bus.master
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self.sp810_fake.pio = bus.master
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self.watchdog_fake.pio = bus.master
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self.gpio0_fake.pio = bus.master
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self.gpio1_fake.pio = bus.master
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self.gpio2_fake.pio = bus.master
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self.ssp_fake.pio = bus.master
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self.sci_fake.pio = bus.master
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self.aaci_fake.pio = bus.master
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self.mmc_fake.pio = bus.master
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self.rtc_fake.pio = bus.master
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self.flash_fake.pio = bus.master
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self.smcreg_fake.pio = bus.master
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self.energy_ctrl.pio = bus.master
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# Set the clock domain for IO objects that are considered
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# to be "far" away from the cores.
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def offChipIOClkDomain(self, clkdomain):
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self.uart.clk_domain = clkdomain
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self.realview_io.clk_domain = clkdomain
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self.timer0.clk_domain = clkdomain
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self.timer1.clk_domain = clkdomain
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self.clcd.clk_domain = clkdomain
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self.kmi0.clk_domain = clkdomain
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self.kmi1.clk_domain = clkdomain
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self.dmac_fake.clk_domain = clkdomain
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self.uart1_fake.clk_domain = clkdomain
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self.uart2_fake.clk_domain = clkdomain
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self.uart3_fake.clk_domain = clkdomain
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self.smc_fake.clk_domain = clkdomain
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self.sp810_fake.clk_domain = clkdomain
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self.watchdog_fake.clk_domain = clkdomain
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self.gpio0_fake.clk_domain = clkdomain
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self.gpio1_fake.clk_domain = clkdomain
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self.gpio2_fake.clk_domain = clkdomain
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self.ssp_fake.clk_domain = clkdomain
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self.sci_fake.clk_domain = clkdomain
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self.aaci_fake.clk_domain = clkdomain
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self.mmc_fake.clk_domain = clkdomain
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self.rtc.clk_domain = clkdomain
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self.flash_fake.clk_domain = clkdomain
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self.smcreg_fake.clk_domain = clkdomain
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self.energy_ctrl.clk_domain = clkdomain
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class VExpress_EMM(RealView):
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_mem_regions = [(Addr('2GB'), Addr('2GB'))]
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