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misc: Merge release-staging-v23-1 into stable (#711)

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This commit is contained in:
Bobby R. Bruce
2023-12-28 12:50:12 -08:00
committed by GitHub
parent 461af51575 e0706e9270
commit bae3487678
1525 changed files with 50224 additions and 13545 deletions
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6
.git-blame-ignore-revs
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@@ -29,3 +29,9 @@ c3bd8eb1214cbebbc92c7958b80aa06913bce3ba
# A commit which ran flynt all Python files.
e73655d038cdfa68964109044e33c9a6e7d85ac9
# A commit which ran pre-commit on ext/testlib
9e1afdecefaf910fa6e266f29dc480a32b0fa83e
# Updated black from 22.6.0 to 23.9.1
ddf6cb88e48df4ac7de4a9e4b612daf2e7e635c8

2
.gitignore vendored
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@@ -1,4 +1,5 @@
build
gem5_build
parser.out
parsetab.py
cscope.files
@@ -32,3 +33,4 @@ configs/example/memcheck.cfg
configs/dram/lowp_sweep.cfg
.pyenv
.vscode
typings

113
.pre-commit-config.yaml
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@@ -1,3 +1,4 @@
---
# Copyright (c) 2022 Arm Limited
# All rights reserved.
#
@@ -33,57 +34,77 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
minimum_pre_commit_version: "2.18"
minimum_pre_commit_version: '2.18'
default_language_version:
python: python3
python: python3
exclude: |
(?x)^(
ext/.*|
build/.*|
src/systemc/ext/.*|
src/systemc/tests/.*/.*|
src/python/m5/ext/pyfdt/.*|
tests/.*/ref/.*
)$
(?x)^(
ext/(?!testlib/).*|
build/.*|
src/systemc/ext/.*|
src/systemc/tests/.*/.*|
src/python/m5/ext/pyfdt/.*|
tests/.*/ref/.*
)$
default_stages: [commit]
repos:
- repo: https://github.com/pre-commit/pre-commit-hooks
rev: v4.3.0
hooks:
- id: trailing-whitespace
- id: end-of-file-fixer
- id: check-json
- id: check-yaml
- id: check-added-large-files
- id: mixed-line-ending
args: [--fix=lf]
- id: check-case-conflict
- repo: https://github.com/psf/black
rev: 22.6.0
hooks:
- id: black
- repo: local
hooks:
- id: gem5-style-checker
name: gem5 style checker
entry: util/git-pre-commit.py
always_run: true
exclude: ".*"
language: system
description: 'The gem5 style checker hook.'
- id: gem5-commit-msg-checker
name: gem5 commit msg checker
entry: ext/git-commit-msg
language: system
stages: [commit-msg]
description: 'The gem5 commit message checker hook.'
- id: gerrit-commit-msg-job
name: gerrit commit message job
entry: util/gerrit-commit-msg-hook
language: system
stages: [commit-msg]
description: 'Adds Change-ID to the commit message. Needed by Gerrit.'
- repo: https://github.com/pre-commit/pre-commit-hooks
rev: v4.5.0
hooks:
- id: trailing-whitespace
- id: end-of-file-fixer
- id: check-json
- id: check-yaml
- id: check-added-large-files
- id: mixed-line-ending
args: [--fix=lf]
- id: check-ast
- id: check-case-conflict
- id: check-merge-conflict
- id: check-symlinks
- id: destroyed-symlinks
- id: requirements-txt-fixer
- repo: https://github.com/PyCQA/isort
rev: 5.11.5
hooks:
- id: isort
- repo: https://github.com/jumanjihouse/pre-commit-hook-yamlfmt
rev: 0.2.3
hooks:
- id: yamlfmt
- repo: https://github.com/psf/black
rev: 23.9.1
hooks:
- id: black
- repo: https://github.com/asottile/pyupgrade
rev: v3.14.0
hooks:
- id: pyupgrade
# Python 3.8 is the earliest version supported.
# We therefore conform to the standards compatible with 3.8+.
args: [--py38-plus]
- repo: local
hooks:
- id: gem5-style-checker
name: gem5 style checker
entry: util/git-pre-commit.py
always_run: true
exclude: .*
language: system
description: The gem5 style checker hook.
- id: gem5-commit-msg-checker
name: gem5 commit msg checker
entry: ext/git-commit-msg
language: system
stages: [commit-msg]
description: The gem5 commit message checker hook.
- id: gerrit-commit-msg-job
name: gerrit commit message job
entry: util/gerrit-commit-msg-hook
language: system
stages: [commit-msg]
description: Adds Change-ID to the commit message. Needed by Gerrit.

394
MAINTAINERS.yaml
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@@ -1,23 +1,23 @@
---
# See CONTRIBUTING.md for details of gem5's contribution process.
#
# This file contains a list of gem5's subsystems and their
# maintainers. The key used to identifity a subsystem should be used
# as a tag in commit messages targetting that subsystem. At least one
# (not all) of these maintainers must review the patch before it can
# be pushed. These people will automatically be emailed when you
# upload the patch to Gerrit (https://gem5-review.googlesource.com).
# These subsystem keys mostly follow the directory structure.
# maintainers. The key used to identify a subsystem should be used
# as a tag in commit messages targeting that subsystem. Via our GitHub
# Pull Request system (https://github.com/gem5/gem5/pulls) a maintainer
# of the subsystem impacted by a pull request contribution will be added
# as an assignee to that pull request. Their role is be to referee the
# contribution (add a review, assign reviewers, suggest changes, etc.), then
# merge the contribution into the gem5 develop branch when they are satisfied
# with the change.
#
# Maintainers have the following responsibilities:
# 1. That at least one maintainer of each subsystem reviews all
# changes to that subsystem (they will be automatically tagged and
# emailed on each new change).
# 2. They will complete your reviews in a timely manner (within a few
# business days).
# 3. They pledge to uphold gem5's community standards and its code of
# conduct by being polite and professional in their code
# reviews. See CODE-OF-CONDUCT.md.
# Maintainers assigned to a pull request are expected to acknowledge their
# assignment in 2 business days and to fully begin refereeing the contribution
# within a business week.
#
# Maintainers pledge to uphold gem5's community standards and its code of
# conduct by being polite and professional in their interactions with
# contributors. See CODE-OF-CONDUCT.md.
#
# Entries in this file have the following format:
# key:
@@ -27,310 +27,260 @@
# maintainers:
# - John Doe <john.doe@gem5.org>
# - Jane Doe <jane.doe@gem5.org>
#
# experts:
# - Jack Doe <jack.doe@gem5org>
# - Jill Doe <jill.doe@gem5org>
#
# The status field should have one of the following values:
# - maintained: The component has an active maintainer.
# - orphaned: The component is looking for a new owner.
pmc:
desc: >-
PMC Members (general maintainers):
status: maintained
maintainers:
- Andreas Sandberg <andreas.sandberg@arm.com>
- Brad Beckmann <bradford.beckmann@gmail.com>
- David Wood <david@cs.wisc.edu>
- Gabe Black <gabe.black@gmail.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>
- Jason Lowe-Power <jason@lowepower.com> (chair)
- Matt Sinclair <sinclair@cs.wisc.edu>
- Tony Gutierrez <anthony.gutierrez@amd.com>
- Steve Reinhardt <stever@gmail.com>
#
# The experts field is optional and used to identify people who are
# knowledgeable about the subsystem but are not responsible for it. Those
# listed as an expert are typically good to add as a reviewer for pull requests
# targeting that subsystem.
arch:
desc: >-
General architecture-specific components
status: maintained
maintainers:
- Gabe Black <gabe.black@gmail.com>
desc: >-
General architecture-specific components
status: orphaned
arch-arm:
status: maintained
maintainers:
- Andreas Sandberg <andreas.sandberg@arm.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>
status: maintained
maintainers:
- Giacomo Travaglini <giacomo.travaglini@arm.com>
- Andreas Sandberg <andreas.sandberg@arm.com>
arch-gcn3:
status: maintained
maintainers:
- Matt Poremba <matthew.poremba@amd.com>
- Matt Sinclair <sinclair@cs.wisc.edu>
status: maintained
maintainers:
- Matt Sinclair <sinclair@cs.wisc.edu>
- Matt Poremba <matthew.poremba@amd.com>
arch-vega:
status: maintained
maintainers:
- Matt Poremba <matthew.poremba@amd.com>
- Matt Sinclair <sinclair@cs.wisc.edu>
status: maintained
maintainers:
- Matt Sinclair <sinclair@cs.wisc.edu>
- Matt Poremba <matthew.poremba@amd.com>
arch-mips:
status: orphaned
status: orphaned
arch-power:
status: maintained
maintainers:
- Boris Shingarov <shingarov@labware.com>
status: orphaned
arch-riscv:
status: orphaned
status: orphaned
arch-sparc:
status: maintained
maintainers:
- Gabe Black <gabe.black@gmail.com>
status: orphaned
arch-x86:
status: maintained
maintainers:
- Gabe Black <gabe.black@gmail.com>
status: orphaned
base:
status: maintained
maintainers:
- Bobby Bruce <bbruce@ucdavis.edu>
- Daniel Carvalho <odanrc@yahoo.com.br>
status: orphaned
base-stats:
status: orphaned
status: orphaned
configs:
status: maintained
maintainers:
- Jason Lowe-Power <jason@lowepower.com>
status: orphaned
experts:
- Jason Lowe-Power <jason@lowepower.com>
cpu:
desc: >-
General changes to all CPU models (e.g., BaseCPU)
status: maintained
maintainers:
- Gabe Black <gabe.black@gmail.com>
- Jason Lowe-Power <jason@lowepower.com>
desc: >-
General changes to all CPU models (e.g., BaseCPU)
status: orphaned
experts:
- Jason Lowe-Power <jason@lowepower.com>
cpu-kvm:
status: maintained
maintainers:
- Andreas Sandberg <andreas.sandberg@arm.com>
status: maintained
maintainers:
- Andreas Sandberg <andreas.sandberg@arm.com>
cpu-minor:
status: maintained
maintainers:
- Zhengrong Wang <seanyukigeek@gmail.com>
status: orphaned
cpu-o3:
status: orphaned
status: orphaned
cpu-simple:
status: maintained
maintainers:
- Jason Lowe-Power <jason@lowepower.com>
- Gabe Black <gabe.black@gmail.com>
status: orphaned
experts:
- Jason Lowe-Power <jason@lowepower.com>
dev:
status: maintained
maintainers:
- Gabe Black <gabe.black@gmail.com>
status: orphaned
dev-hsa:
status: maintained
maintainers:
- Matt Poremba <matthew.poremba@amd.com>
status: maintained
maintainers:
- Matt Poremba <matthew.poremba@amd.com>
dev-amdgpu:
status: maintained
maintainers:
- Matt Poremba <matthew.poremba@amd.com>
status: maintained
maintainers:
- Matt Poremba <matthew.poremba@amd.com>
dev-virtio:
status: maintained
maintainers:
- Andreas Sandberg <andreas.sandberg@arm.com>
status: maintained
maintainers:
- Andreas Sandberg <andreas.sandberg@arm.com>
dev-arm:
status: maintained
maintainers:
- Andreas Sandberg <andreas.sandberg@arm.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>
status: maintained
maintainers:
- Giacomo Travaglini <giacomo.travaglini@arm.com>
- Andreas Sandberg <andreas.sandberg@arm.com>
doc:
status: maintained
maintainers:
- Bobby Bruce <bbruce@ucdavis.edu>
status: orphaned
ext:
desc: >-
Components external to gem5
status: maintained
maintainers:
- Bobby Bruce <bbruce@ucdavis.edu>
- Jason Lowe-Power <jason@lowepower.com>
desc: >-
Components external to gem5
status: orphaned
experts:
- Jason Lowe-Power <jason@lowepower.com>
ext-testlib:
status: maintained
maintainers:
- Bobby Bruce <bbruce@ucdavis.edu>
- Hoa Nguyen <hoanguyen@ucdavis.edu>
status: orphaned
experts:
- Bobby R. Bruce <bbruce@ucdavis.edu>
fastmodel:
desc: >-
Changes relating to ARM Fast Models
status: maintained
maintainers:
- Gabe Black <gabe.black@gmail.com>
desc: >-
Changes relating to ARM Fast Models
status: orphaned
gpu-compute:
status: maintained
maintainers:
- Matt Poremba <matthew.poremba@amd.com>
- Matt Sinclair <sinclair@cs.wisc.edu>
status: maintained
maintainers:
- Matt Poremba <matthew.poremba@amd.com>
learning-gem5:
desc: >-
The code and configs for the Learning gem5 book
status: maintained
maintainers:
- Jason Lowe-Power <jason@lowepower.com>
desc: >-
The code and configs for the Learning gem5 book
status: orphaned
experts:
- Jason Lowe-Power <jason@lowepower.com>
- Bobby R. Bruce <bbruce@ucdavis.edu>
stdlib:
desc: >-
The gem5 standard library found under `src/python/gem5`
status: maintained
maintainers:
- Bobby R. Bruce <bbruce@ucdavis.edu>
desc: >-
The gem5 standard library found under `src/python/gem5`
status: maintained
maintainers:
- Bobby R. Bruce <bbruce@ucdavis.edu>
mem:
desc: >-
General memory system (e.g., XBar, Packet)
status: maintained
maintainers:
- Nikos Nikoleris <nikos.nikoleris@arm.com>
desc: >-
General memory system (e.g., XBar, Packet)
status: orphaned
mem-cache:
desc: >-
Classic caches and coherence
status: maintained
maintainers:
- Nikos Nikoleris <nikos.nikoleris@arm.com>
- Daniel Carvalho <odanrc@yahoo.com.br>
desc: >-
Classic caches and coherence
status: orphaned
mem-dram:
status: maintained
maintainers:
- Nikos Nikoleris <nikos.nikoleris@arm.com>
status: orphaned
mem-garnet:
desc: >-
Garnet subcomponent of Ruby
status: maintained
maintainers:
- Srikant Bharadwaj <srikant.bharadwaj@amd.com>
desc: >-
Garnet subcomponent of Ruby
status: orphaned
mem-ruby:
desc: >-
Ruby structures and protocols
status: maintained
maintainers:
- Jason Lowe-Power <jason@lowepower.com>
- Matt Sinclair <sinclair@cs.wisc.edu>
desc: >-
Ruby structures and protocols
status: maintained
maintainers:
- Matt Sinclair <sinclair@cs.wisc.edu>
experts:
- Jason Lowe-Power <jason@lowepower.com>
misc:
desc: >-
Anything outside of the other categories
status: maintained
maintainers:
- Bobby Bruce <bbruce@ucdavis.edu>
- Jason Lowe-Power <jason@lowepower.com>
desc: >-
Anything outside of the other categories
status: orphaned
experts:
- Jason Lowe-Power <jason@lowepower.com>
python:
desc: >-
Python SimObject wrapping and infrastructure
status: maintained
maintainers:
- Andreas Sandberg <andreas.sandberg@arm.com>
- Jason Lowe-Power <jason@lowepower.com>
desc: >-
Python SimObject wrapping and infrastructure
status: orphaned
experts:
- Jason Lowe-Power <jason@lowepower.com>
- Andreas Sandberg <andreas.sandberg@arm.com>
resources:
desc: >-
The gem5-resources repo with auxiliary resources for simulation
status: maintained
maintainers:
- Bobby Bruce <bbruce@ucdavis.edu>
- Jason Lowe-Power <jason@lowepower.com>
desc: >-
The gem5-resources repo with auxiliary resources for simulation
status: maintained
maintainers:
- Bobby R. Bruce <bbruce@ucdavis.edu>
experts:
- Jason Lowe-Power <jason@lowepower.com>
scons:
desc: >-
Build system
status: maintained
maintainers:
- Gabe Black <gabe.black@gmail.com>
desc: >-
Build system
status: orphaned
sim:
desc: >-
General simulation components
status: maintained
maintainers:
- Jason Lowe-Power <jason@lowepower.com>
desc: >-
General simulation components
status: orphaned
experts:
- Jason Lowe-Power <jason@lowepower.com>
sim-se:
desc: >-
Syscall emulation
status: orphaned
desc: >-
Syscall emulation
status: orphaned
system-arm:
status: maintained
maintainers:
- Andreas Sandberg <andreas.sandberg@arm.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>
status: maintained
maintainers:
- Giacomo Travaglini <giacomo.travaglini@arm.com>
- Andreas Sandberg <andreas.sandberg@arm.com>
systemc:
desc: >-
Code for the gem5 SystemC implementation and interface
status: maintained
maintainers:
- Gabe Black <gabe.black@gmail.com>
desc: >-
Code for the gem5 SystemC implementation and interface
status: orphaned
tests:
desc: >-
testing changes
status: maintained
maintainers:
- Bobby Bruce <bbruce@ucdavis.edu>
desc: >-
testing changes
status: maintained
maintainers:
- Bobby R. Bruce <bbruce@ucdavis.edu>
util:
status: maintained
maintainers:
- Gabe Black <gabe.black@gmail.com>
status: orphaned
util-docker:
status: maintained
maintainers:
- Bobby Bruce <bbruce@ucdavis.edu>
status: maintained
maintainers:
- Bobby R. Bruce <bbruce@ucdavis.edu>
util-m5:
status: maintained
maintainers:
- Gabe Black <gabe.black@gmail.com>
status: orphaned
util-gem5art:
status: maintained
maintainers:
- Bobby Bruce <bbruce@ucdavis.edu>
- Jason Lowe-Power <jason@lowepower.com>
status: orphaned
website:
desc: >-
The gem5-website repo which contains the gem5.org site
status: maintained
maintainers:
- Bobby Bruce <bbruce@ucdavis.edu>
- Hoa Nguyen <hoanguyen@ucdavis.edu>
desc: >-
The gem5-website repo which contains the gem5.org site
status: maintained
maintainers:
- Bobby R. Bruce <bbruce@ucdavis.edu>
experts:
- Jason Lowe-Power <jason@lowepower.com>

13
README.md
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@@ -10,6 +10,15 @@ system software changes, and compile-time and run-time system optimizations.
The main website can be found at <http://www.gem5.org>.
## Testing status
**Note**: These regard tests run on the develop branch of gem5:
<https://github.com/gem5/gem5/tree/develop>.
[![Daily Tests](https://github.com/gem5/gem5/actions/workflows/daily-tests.yaml/badge.svg)](https://github.com/gem5/gem5/actions/workflows/daily-tests.yaml)
[![Weekly Tests](https://github.com/gem5/gem5/actions/workflows/weekly-tests.yaml/badge.svg)](https://github.com/gem5/gem5/actions/workflows/weekly-tests.yaml)
[![Compiler Tests](https://github.com/gem5/gem5/actions/workflows/compiler-tests.yaml/badge.svg)](https://github.com/gem5/gem5/actions/workflows/compiler-tests.yaml)
## Getting started
A good starting point is <http://www.gem5.org/about>, and for
@@ -29,8 +38,8 @@ Once you have all dependencies resolved, execute
`scons build/ALL/gem5.opt` to build an optimized version of the gem5 binary
(`gem5.opt`) containing all gem5 ISAs. If you only wish to compile gem5 to
include a single ISA, you can replace `ALL` with the name of the ISA. Valid
options include `ARM`, `NULL`, `MIPS`, `POWER`, `SPARC`, and `X86` The complete
list of options can be found in the build_opts directory.
options include `ARM`, `NULL`, `MIPS`, `POWER`, `RISCV`, `SPARC`, and `X86`
The complete list of options can be found in the build_opts directory.
See https://www.gem5.org/documentation/general_docs/building for more
information on building gem5.

130
RELEASE-NOTES.md
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@@ -1,3 +1,133 @@
# Version 23.1
gem5 Version 23.1 is our first release where the development has been on GitHub.
During this release, there have been 362 pull requests merged which comprise 416 commits with 51 unique contributors.
## Significant API and user-facing changes
### The gem5 build can is now configured with `kconfig`
- Most gem5 builds without customized options (excluding double dash options) (e.g. , build/X86/gem5.opt) are backwards compatible and require no changes to your current workflows.
- All of the default builds in `build_opts` are unchanged and still available.
- However, if you want to specialize your build. For example, use customized ruby protocol. The command `scons PROTOCOL=<PROTOCAL_NAME> build/ALL/gem5.opt` will not work anymore. you now have to use `scons <kconfig command>` to update the ruby protocol as example. The double dash options (`--without-tcmalloc`, `--with-asan` and so on) are still continue to work as normal.
- For more details refer to the documentation here: [kconfig documentation](https://www.gem5.org/documentation/general_docs/kconfig_build_system/)
### Standard library improvements
#### `WorkloadResource` added to resource specialization
- The `Workload` and `CustomWorkload` classes are now deprecated. They have been transformed into wrappers for the `obtain_resource` and `WorkloadResource` classes in `resource.py`, respectively.
- Code utilizing the older API will continue to function as expected but will trigger a warning message. To update code using the `Workload` class, change the call from `Workload(id='resource_id', resource_version='1.0.0')` to `obtain_resource(id='resource_id', resource_version='1.0.0')`. Similarly, to update code using the `CustomWorkload` class, change the call from `CustomWorkload(function=func, parameters=params)` to `WorkloadResource(function=func, parameters=params)`.
- Workload resources in gem5 can now be directly acquired using the `obtain_resource` function, just like other resources.
#### Introducing Suites
Suites is a new category of resource being introduced in gem5. Documentation of suites can be found here: [suite documentation](https://www.gem5.org/documentation/gem5-stdlib/suites).
#### Other API changes
- All resource object now have their own `id` and `category`. Each resource class has its own `__str__()` function which return its information in the form of **category(id, version)** like **BinaryResource(id='riscv-hello', resource_version='1.0.0')**.
- Users can use GEM5_RESOURCE_JSON and GEM5_RESOURCE_JSON_APPEND env variables to overwrite all the data sources with the provided JSON and append a JSON file to all the data source respectively. More information can be found [here](https://www.gem5.org/documentation/gem5-stdlib/using-local-resources).
### Other user-facing changes
- Added support for clang 15 and clang 16
- gem5 no longer supports building on Ubuntu 18.04
- GCC 7, GCC 9, and clang 6 are no longer supported
- Two `DRAMInterface` stats have changed names (`bytesRead` and `bytesWritten`). For instance, `board.memory.mem_ctrl.dram.bytesRead` and `board.memory.mem_ctrl.dram.bytesWritten`. These are changed to `dramBytesRead` and `dramBytesWritten` so they don't collide with the stat with the same name in `AbstractMemory`.
- The stats for `NVMInterface` (`bytesRead` and `bytesWritten`) have been change to `nvmBytesRead` and `nvmBytesWritten` as well.
## Full-system GPU model improvements
- Support for up to latest ROCm 5.7.1.
- Various changes to enable PyTorch/TensorFlow simulations.
- New packer disk image script containing ROCm 5.4.2, PyTorch 2.0.1, and Tensorflow 2.11.
- GPU instructions can now perform atomics on host addresses.
- The provided configs scripts can now run KVM on more restrictive setups.
- Add support to checkpoint and restore between kernels in GPUFS, including adding various AQL, HSA Queue, VMID map, MQD attributes, GART translations, and PM4Queues to GPU checkpoints
- move GPU cache recorder code to RubyPort instead of Sequencer/GPUCoalescer to allow checkpointing to occur
- add support for flushing GPU caches, as well as cache cooldown/warmup support, for checkpoints
- Update vega10_kvm.py to add checkpointing instructions
## SE mode GPU model improvements
- started adding support for mmap'ing inputs for GPUSE tests, which reduces their runtime by 8-15% per run
## GPU model improvements
- update GPU VIPER and Coalescer support to ensure correct replacement policy behavior when multiple requests from the same CU are concurrently accessing the same line
- fix bug with GPU VIPER to resolve a race conflict for loads that bypass the TCP (L1D$)
- fix bug with MRU replacement policy updates in GPU SQC (I$)
- update GPU and Ruby debug prints to resolve various small errors
- Add configurable GPU L1,L2 num banks and L2 latencies
- Add decodings for new MI100 VOP2 insts
- Add GPU GLC Atomic Resource Constraints to better model how atomic resources are shared at GPU TCC (L2$)
- Update GPU tester to work with both requests that bypass all caches (SLC) and requests that bypass only the TCP (L1D$)
- Fixes for how write mask works for GPU WB L2 caches
- Added support for WB and WT GPU atomics
- Added configurable support to better model the latency of GPU atomic requests
- fix GPU's default number of HW barrier/CU to better model amount of concurrency GPU CUs should have
## RISC-V RVV 1.0 implemented
This was a huge undertaking by a large number of people!
Some of these people include Adrià Armejach who pushed it over the finish line, Xuan Hu who pushed the most recent version to gerrit that Adrià picked up,
Jerin Joy who did much of the initial work, and many others who contributed to the implementation including Roger Chang, Hoa Nguyen who put significant effort into testing and reviewing the code.
- Most of the instructions in the 1.0 spec implemented
- Works with both FS and SE mode
- Compatible with Simple CPUs, the O3, and the minor CPU models
- User can specify the width of the vector units
- Future improvements
- Widening/narrowing instructions are *not* implemented
- The model for executing memory instructions is not very high performance
- The statistics are not correct for counting vector instruction execution
## ArmISA changes/improvements
- Architectural support for the following extensions:
* FEAT_TLBIRANGE
* FEAT_FGT
* FEAT_TCR2
* FEAT_SCTLR2
- Arm support for SVE instructions improved
- Fixed some FEAT_SEL2 related issues:
- [Fix virtual interrupt logic in secure mode](https://github.com/gem5/gem5/pull/584)
- [Make interrupt masking handle VHE/SEL2 cases](https://github.com/gem5/gem5/pull/430)
- Removed support for Arm Jazelle and ThumbEE
- Implementation of an Arm Capstone Disassembler
## Other notable changes/improvements
- Improvements to the CHI coherence protocol implementation
- Far atomics implemented in CHI
- Ruby now supports using the prefetchers from the classic caches, if the protocol supports it. CHI has been extended to support the classic prefetchers.
- Bug in RISC-V TLB to fixed to correctly count misses and hits
- Added new RISC-V Zcb instructions https://github.com/gem5/gem5/pull/399
- RISC-V can now use a separate binary for the bootloader and kernel in FS mode
- DRAMSys integration updated to latest DRAMSys version (5.0)
- Improved support for RISC-V privilege modes
- Fixed bug in switching CPUs with RISC-V
- CPU branch preditor refactoring to prepare for decoupled front end support
- Perf is now optional when using the KVM CPU model
- Improvements to the gem5-SST bridge including updating to SST 13.0
- Improved formatting of documentation in stdlib
- By default use isort for python imports in style
- Many, many testing improvements during the migration to GitHub actions
- Fixed the elastic trace replaying logic (TraceCPU)
## Known Bugs/Issues
- [RISC-V RVV Bad execution of riscv rvv vss instruction](https://github.com/gem5/gem5/issues/594)
- [RISC-V Vector Extension float32_t bugs/unsupported widening instructions](https://github.com/gem5/gem5/issues/442)
- [Implement AVX xsave/xstor to avoid workaround when checkpointing](https://github.com/gem5/gem5/issues/434)
- [Adding Vector Segmented Loads/Stores to RISC-V V 1.0 implementation](https://github.com/gem5/gem5/issues/382)
- [Integer overflow in AddrRange subset check](https://github.com/gem5/gem5/issues/240)
- [RISCV64 TLB refuses to access upper half of physical address space](https://github.com/gem5/gem5/issues/238)
- [Bug when trying to restore checkpoints in SPARC: “panic: panic condition !pte occurred: Tried to execute unmapped address 0.”](https://github.com/gem5/gem5/issues/197)
- [BaseCache::recvTimingResp can trigger an assertion error from getTarget() due to MSHR in senderState having no targets](https://github.com/gem5/gem5/issues/100)
# Version 23.0.1.0
This minor release incorporates documentation updates, bug fixes, and some minor improvements.

53
SConsopts
View File

@@ -1,53 +0,0 @@
# Copyright (c) 2013, 2015-2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2011 Advanced Micro Devices, Inc.
# Copyright (c) 2009 The Hewlett-Packard Development Company
# Copyright (c) 2004-2005 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os
import os.path
from gem5_scons import warning
Import('*')
sticky_vars.AddVariables(
('BATCH', 'Use batch pool for build and tests', False),
('BATCH_CMD', 'Batch pool submission command name', 'qdo'),
('M5_BUILD_CACHE', 'Cache built objects in this directory', False),
('USE_EFENCE', 'Link with Electric Fence malloc debugger', False),
)

380
SConstruct
View File

@@ -44,15 +44,6 @@
#
# SCons top-level build description (SConstruct) file.
#
# While in this directory ('gem5'), just type 'scons' to build the default
# configuration (see below), or type 'scons build/<CONFIG>/<binary>'
# to build some other configuration (e.g., 'build/X86/gem5.opt' for
# the optimized X86 version).
#
# You can build gem5 in a different directory as long as there is a
# 'build/<CONFIG>' somewhere along the target path. The build system
# expects that all configs under the same build directory are being
# built for the same host system.
#
# Examples:
#
@@ -77,10 +68,11 @@
# Global Python imports
import atexit
import itertools
import os
import sys
from os import mkdir, remove, environ
from os import mkdir, remove, environ, listdir
from os.path import abspath, dirname, expanduser
from os.path import isdir, isfile
from os.path import join, split
@@ -115,8 +107,6 @@ AddOption('--no-colors', dest='use_colors', action='store_false',
help="Don't add color to abbreviated scons output")
AddOption('--with-cxx-config', action='store_true',
help="Build with support for C++-based configuration")
AddOption('--default',
help='Override which build_opts file to use for defaults')
AddOption('--ignore-style', action='store_true',
help='Disable style checking hooks')
AddOption('--linker', action='store', default=None, choices=linker_options,
@@ -141,6 +131,8 @@ AddOption('--with-systemc-tests', action='store_true',
help='Build systemc tests')
AddOption('--install-hooks', action='store_true',
help='Install revision control hooks non-interactively')
AddOption('--limit-ld-memory-usage', action='store_true',
help='Tell ld, the linker, to reduce memory usage.')
AddOption('--gprof', action='store_true',
help='Enable support for the gprof profiler')
AddOption('--pprof', action='store_true',
@@ -162,6 +154,7 @@ sys.path[1:1] = [ Dir('#build_tools').abspath ]
# declared above.
from gem5_scons import error, warning, summarize_warnings, parse_build_path
from gem5_scons import TempFileSpawn, EnvDefaults, MakeAction, MakeActionTool
from gem5_scons import kconfig
import gem5_scons
from gem5_scons.builders import ConfigFile, AddLocalRPATH, SwitchingHeaders
from gem5_scons.builders import Blob
@@ -205,7 +198,71 @@ if not ('CC' in main and 'CXX' in main):
error("No C++ compiler installed (package g++ on Ubuntu and RedHat)")
# Find default configuration & binary.
Default(environ.get('M5_DEFAULT_BINARY', 'build/ARM/gem5.debug'))
default_target = environ.get('M5_DEFAULT_BINARY', None)
if default_target:
Default(default_target)
# If no target is set, even a default, print help instead.
if not BUILD_TARGETS:
warning("No target specified, and no default.")
SetOption('help', True)
buildopts_dir = Dir('#build_opts')
buildopts = list([f for f in os.listdir(buildopts_dir.abspath) if
isfile(os.path.join(buildopts_dir.abspath, f))])
buildopts.sort()
buildopt_list = '\n'.join(' ' * 10 + buildopt for buildopt in buildopts)
Help(f"""
Targets:
To build gem5 using a predefined configuration, use a target with
a directory called "build" in the path, followed by a directory named
after a predefined configuration in "build_opts" directory, and then
the actual target, likely a gem5 binary. For example:
scons build/ALL/gem5.opt
The "build" component tells SCons that the next part names an initial
configuration, and the part after that is the actual target.
The predefined targets currently available are:
{buildopt_list}
The extension on the gem5 binary specifies what type of binary to
build. Options are:
debug: A debug binary with optimizations turned off and debug info
turned on.
opt: An optimized binary with debugging still turned on.
fast: An optimized binary with debugging, asserts, and tracing
disabled.
gem5 can also be built as a static or dynamic library. In that case,
the extension is determined by the operating system, so the binary type
is part of the target file name. For example:
scons build/ARM/libgem5_opt.so
In MacOS, the extension should change to "dylib" like this:
scons build/ARM/libgem5_opt.dylib
To build unit tests, you can use a target like this:
scons build/RISCV/unittests.debug
The unittests.debug part of the target is actual a directory which
holds the results for all the unit tests built with the "debug"
settings. When that's used as the target, SCons will build all the
files under that directory, which will run all the tests.
To build and run an individual test, you can built it's binary
specifically and then run it manually:
scons build/SPARC/base/bitunion.test.opt
build/SPARC/base/bitunion.test.opt
""", append=True)
########################################################################
@@ -215,52 +272,134 @@ Default(environ.get('M5_DEFAULT_BINARY', 'build/ARM/gem5.debug'))
#
########################################################################
# helper function: find last occurrence of element in list
def rfind(l, elt, offs = -1):
for i in range(len(l)+offs, 0, -1):
if l[i] == elt:
return i
raise ValueError("element not found")
kconfig_actions = (
'defconfig',
'guiconfig',
'listnewconfig',
'menuconfig',
'oldconfig',
'olddefconfig',
'savedefconfig',
'setconfig',
)
Help("""
Kconfig:
In addition to the default configs, you can also create your own
configs, or edit one that already exists. To use one of the kconfig
tools with a particular directory, use a target which is the directory
to configure, and then the name of the tool. For example, to run
menuconfig on directory build_foo/bar, run:
scons menuconfig build_foo/bar
will set up a build directory in build_foo/bar if one doesn't already
exist, and open the menuconfig editor to view/set configuration
values.
Kconfig tools:
defconfig:
Set up a config using values specified in a defconfig file, or if no
value is given, use the default. The second argument specifies the
defconfig file. A defconfig file in the build_opts directory can be
implicitly specified in the build path via `build/<defconfig file>/`
scons defconfig build_foo/bar build_opts/MIPS
guiconfig:
Opens the guiconfig editor which will let you view and edit config
values, and view help text. guiconfig runs as a graphical application.
scons guiconfig build_foo/bar
listnewconfig:
Lists config options which are new in the Kconfig and which are not
currently set in the existing config file.
scons listnewconfig build_foo/bar
menuconfig:
Opens the menuconfig editor which will let you view and edit config
values, and view help text. menuconfig runs in text mode.
scons menuconfig build_foo/bar
oldconfig:
Update an existing config by adding settings for new options. This is
the same as the olddefconfig tool, except it asks what values you want
for the new settings.
scons oldconfig build_foo/bar
olddefconfig:
Update an existing config by adding settings for new options. This is
the same as the oldconfig tool, except it uses the default for any new
setting.
scons olddefconfig build_foo/bar
savedefconfig:
Save a defconfig file which would give rise to the current config.
For instance, you could use menuconfig to set up a config how you want
it with the options you cared about, and then use savedefconfig to save
a minimal config file. These files would be suitable to use in the
defconfig directory. The second argument specifies the filename for
the new defconfig file.
scons savedefconfig build_foo/bar new_def_config
setconfig:
Set values in an existing config directory as specified on the command
line. For example, to enable gem5's built in systemc kernel:
scons setconfig build_foo/bar USE_SYSTEMC=y
""", append=True)
# Take a list of paths (or SCons Nodes) and return a list with all
# paths made absolute and ~-expanded. Paths will be interpreted
# relative to the launch directory unless a different root is provided
def makePathAbsolute(path, root=GetLaunchDir()):
return abspath(os.path.join(root, expanduser(str(path))))
def makePathListAbsolute(path_list, root=GetLaunchDir()):
return [abspath(os.path.join(root, expanduser(str(p))))
for p in path_list]
return [makePathAbsolute(p, root) for p in path_list]
# Each target must have 'build' in the interior of the path; the
# directory below this will determine the build parameters. For
# example, for target 'foo/bar/build/X86/arch/x86/blah.do' we
# recognize that X86 specifies the configuration because it
# follow 'build' in the build path.
if BUILD_TARGETS and BUILD_TARGETS[0] in kconfig_actions:
# The build targets are really arguments for the kconfig action.
kconfig_args = BUILD_TARGETS[:]
BUILD_TARGETS[:] = []
# The funky assignment to "[:]" is needed to replace the list contents
# in place rather than reassign the symbol to a new list, which
# doesn't work (obviously!).
BUILD_TARGETS[:] = makePathListAbsolute(BUILD_TARGETS)
kconfig_action = kconfig_args[0]
if len(kconfig_args) < 2:
error(f'Missing arguments for kconfig action {kconfig_action}')
dir_to_configure = makePathAbsolute(kconfig_args[1])
# Generate a list of the unique build roots and configs that the
# collected targets reference.
variant_paths = set()
build_root = None
for t in BUILD_TARGETS:
this_build_root, variant = parse_build_path(t)
kconfig_args = kconfig_args[2:]
# Make sure all targets use the same build root.
if not build_root:
build_root = this_build_root
elif this_build_root != build_root:
error("build targets not under same build root\n %s\n %s" %
(build_root, this_build_root))
variant_paths = {dir_to_configure}
else:
# Each target must have 'build' in the interior of the path; the
# directory below this will determine the build parameters. For
# example, for target 'foo/bar/build/X86/arch/x86/blah.do' we
# recognize that X86 specifies the configuration because it
# follow 'build' in the build path.
# Collect all the variants into a set.
variant_paths.add(os.path.join('/', build_root, variant))
# The funky assignment to "[:]" is needed to replace the list contents
# in place rather than reassign the symbol to a new list, which
# doesn't work (obviously!).
BUILD_TARGETS[:] = makePathListAbsolute(BUILD_TARGETS)
# Make sure build_root exists (might not if this is the first build there)
if not isdir(build_root):
mkdir(build_root)
main['BUILDROOT'] = build_root
# Generate a list of the unique build directories that the collected
# targets reference.
variant_paths = set(map(parse_build_path, BUILD_TARGETS))
kconfig_action = None
########################################################################
@@ -395,10 +534,14 @@ for variant_path in variant_paths:
env = main.Clone()
env['BUILDDIR'] = variant_path
gem5_build = os.path.join(build_root, variant_path, 'gem5.build')
gem5_build = os.path.join(variant_path, 'gem5.build')
env['GEM5BUILD'] = gem5_build
Execute(Mkdir(gem5_build))
config_file = Dir(gem5_build).File('config')
kconfig_file = Dir(gem5_build).File('Kconfig')
gem5_kconfig_file = Dir('#src').File('Kconfig')
env.SConsignFile(os.path.join(gem5_build, 'sconsign'))
# Set up default C++ compiler flags
@@ -447,7 +590,13 @@ for variant_path in variant_paths:
conf.CheckLinkFlag(
'-Wl,--thread-count=%d' % GetOption('num_jobs'))
with gem5_scons.Configure(env) as conf:
ld_optimize_memory_usage = GetOption('limit_ld_memory_usage')
if ld_optimize_memory_usage:
if conf.CheckLinkFlag('-Wl,--no-keep-memory'):
env.Append(LINKFLAGS=['-Wl,--no-keep-memory'])
else:
error("Unable to use --no-keep-memory with the linker")
else:
error('\n'.join((
"Don't know what compiler options to use for your compiler.",
@@ -556,10 +705,14 @@ for variant_path in variant_paths:
if sanitizers:
sanitizers = ','.join(sanitizers)
if env['GCC'] or env['CLANG']:
libsan = (
['-static-libubsan', '-static-libasan']
if env['GCC']
else ['-static-libsan']
)
env.Append(CCFLAGS=['-fsanitize=%s' % sanitizers,
'-fno-omit-frame-pointer'],
LINKFLAGS=['-fsanitize=%s' % sanitizers,
'-static-libasan'])
LINKFLAGS=['-fsanitize=%s' % sanitizers] + libsan)
if main["BIN_TARGET_ARCH"] == "x86_64":
# Sanitizers can enlarge binary size drammatically, north of
@@ -626,7 +779,7 @@ for variant_path in variant_paths:
LINKFLAGS=['-Wl,--no-as-needed', '-lprofiler',
'-Wl,--as-needed'])
env['HAVE_PKG_CONFIG'] = env.Detect('pkg-config')
env['HAVE_PKG_CONFIG'] = env.Detect('pkg-config') == 'pkg-config'
with gem5_scons.Configure(env) as conf:
# On Solaris you need to use libsocket for socket ops
@@ -670,59 +823,13 @@ for variant_path in variant_paths:
after_sconsopts_callbacks.append(cb)
Export('AfterSConsopts')
# Sticky variables get saved in the variables file so they persist from
# one invocation to the next (unless overridden, in which case the new
# value becomes sticky).
sticky_vars = Variables(args=ARGUMENTS)
Export('sticky_vars')
extras_file = os.path.join(gem5_build, 'extras')
extras_var = Variables(extras_file, args=ARGUMENTS)
# EXTRAS is special since it affects what SConsopts need to be read.
sticky_vars.Add(('EXTRAS', 'Add extra directories to the compilation', ''))
# Set env variables according to the build directory config.
sticky_vars.files = []
# Variables for $BUILD_ROOT/$VARIANT_DIR are stored in
# $BUILD_ROOT/$VARIANT_DIR/gem5.build/variables
gem5_build_vars = os.path.join(gem5_build, 'variables')
build_root_vars = os.path.join(build_root, 'variables', variant_dir)
current_vars_files = [gem5_build_vars, build_root_vars]
existing_vars_files = list(filter(isfile, current_vars_files))
if existing_vars_files:
sticky_vars.files.extend(existing_vars_files)
if not GetOption('silent'):
print('Using saved variables file(s) %s' %
', '.join(existing_vars_files))
else:
# Variant specific variables file doesn't exist.
# Get default build variables from source tree. Variables are
# normally determined by name of $VARIANT_DIR, but can be
# overridden by '--default=' arg on command line.
default = GetOption('default')
opts_dir = Dir('#build_opts').abspath
if default:
default_vars_files = [
gem5_build_vars,
build_root_vars,
os.path.join(opts_dir, default)
]
else:
default_vars_files = [os.path.join(opts_dir, variant_dir)]
existing_default_files = list(filter(isfile, default_vars_files))
if existing_default_files:
default_vars_file = existing_default_files[0]
sticky_vars.files.append(default_vars_file)
print("Variables file(s) %s not found,\n using defaults in %s" %
(' or '.join(current_vars_files), default_vars_file))
else:
error("Cannot find variables file(s) %s or default file(s) %s" %
(' or '.join(current_vars_files),
' or '.join(default_vars_files)))
Exit(1)
extras_var.Add(('EXTRAS', 'Add extra directories to the compilation', ''))
# Apply current settings for EXTRAS to env.
sticky_vars.Update(env)
extras_var.Update(env)
# Parse EXTRAS variable to build list of all directories where we're
# look for sources etc. This list is exported as extras_dir_list.
@@ -733,6 +840,17 @@ for variant_path in variant_paths:
Export('extras_dir_list')
# Generate a Kconfig that will source the main gem5 one, and any in any
# EXTRAS directories.
kconfig_base_py = Dir('#build_tools').File('kconfig_base.py')
kconfig_base_cmd_parts = [f'"{kconfig_base_py}" "{kconfig_file.abspath}"',
f'"{gem5_kconfig_file.abspath}"']
for ed in extras_dir_list:
kconfig_base_cmd_parts.append(f'"{ed}"')
kconfig_base_cmd = ' '.join(kconfig_base_cmd_parts)
if env.Execute(kconfig_base_cmd) != 0:
error("Failed to build base Kconfig file")
# Variables which were determined with Configure.
env['CONF'] = {}
@@ -760,24 +878,48 @@ for variant_path in variant_paths:
for cb in after_sconsopts_callbacks:
cb()
# Update env for new variables added by the SConsopts.
sticky_vars.Update(env)
# Handle any requested kconfig action, then exit.
if kconfig_action:
if kconfig_action == 'defconfig':
if len(kconfig_args) != 1:
error('Usage: scons defconfig <build dir> <defconfig file>')
defconfig_path = makePathAbsolute(kconfig_args[0])
kconfig.defconfig(env, kconfig_file.abspath,
defconfig_path, config_file.abspath)
elif kconfig_action == 'guiconfig':
kconfig.guiconfig(env, kconfig_file.abspath, config_file.abspath,
variant_path)
elif kconfig_action == 'listnewconfig':
kconfig.listnewconfig(env, kconfig_file.abspath,
config_file.abspath)
elif kconfig_action == 'menuconfig':
kconfig.menuconfig(env, kconfig_file.abspath, config_file.abspath,
variant_path)
elif kconfig_action == 'oldconfig':
kconfig.oldconfig(env, kconfig_file.abspath, config_file.abspath)
elif kconfig_action == 'olddefconfig':
kconfig.olddefconfig(env, kconfig_file.abspath,
config_file.abspath)
elif kconfig_action == 'savedefconfig':
if len(kconfig_args) != 1:
error('Usage: scons defconfig <build dir> <defconfig file>')
defconfig_path = makePathAbsolute(kconfig_args[0])
kconfig.savedefconfig(env, kconfig_file.abspath,
config_file.abspath, defconfig_path)
elif kconfig_action == 'setconfig':
kconfig.setconfig(env, kconfig_file.abspath, config_file.abspath,
ARGUMENTS)
Exit(0)
Help('''
Build variables for {dir}:
{help}
'''.format(dir=variant_dir, help=sticky_vars.GenerateHelpText(env)),
append=True)
# If no config exists yet, see if we know how to make one?
if not isfile(config_file.abspath):
buildopts_file = Dir('#build_opts').File(variant_dir)
if not isfile(buildopts_file.abspath):
error('No config found, and no implicit config recognized')
kconfig.defconfig(env, kconfig_file.abspath, buildopts_file.abspath,
config_file.abspath)
# If the old vars file exists, delete it to avoid confusion/stale values.
if isfile(build_root_vars):
warning(f'Deleting old variant variables file "{build_root_vars}"')
remove(build_root_vars)
# Save sticky variables back to the gem5.build variant variables file.
sticky_vars.Save(gem5_build_vars, env)
# Pull all the sticky variables into the CONF dict.
env['CONF'].update({key: env[key] for key in sticky_vars.keys()})
kconfig.update_env(env, kconfig_file.abspath, config_file.abspath)
# Do this after we save setting back, or else we'll tack on an
# extra 'qdo' every time we run scons.

16
build_opts/ALL
View File

@@ -1,7 +1,9 @@
USE_ARM_ISA = True
USE_MIPS_ISA = True
USE_POWER_ISA = True
USE_RISCV_ISA = True
USE_SPARC_ISA = True
USE_X86_ISA = True
PROTOCOL = 'MESI_Two_Level'
RUBY=y
RUBY_PROTOCOL_MESI_TWO_LEVEL=y
BUILD_ISA=y
USE_ARM_ISA=y
USE_MIPS_ISA=y
USE_POWER_ISA=y
USE_RISCV_ISA=y
USE_SPARC_ISA=y
USE_X86_ISA=y

6
build_opts/ARM
View File

@@ -1,2 +1,4 @@
USE_ARM_ISA = True
PROTOCOL = 'CHI'
BUILD_ISA=y
USE_ARM_ISA=y
RUBY=y
RUBY_PROTOCOL_CHI=y

9
build_opts/ARM_MESI_Three_Level
View File

@@ -1,5 +1,4 @@
# Copyright (c) 2019 ARM Limited
# All rights reserved.
USE_ARM_ISA = True
PROTOCOL = 'MESI_Three_Level'
BUILD_ISA=y
USE_ARM_ISA=y
RUBY=y
RUBY_PROTOCOL_MESI_THREE_LEVEL=y

9
build_opts/ARM_MESI_Three_Level_HTM
View File

@@ -1,5 +1,4 @@
# Copyright (c) 2019 ARM Limited
# All rights reserved.
USE_ARM_ISA = True
PROTOCOL = 'MESI_Three_Level_HTM'
BUILD_ISA=y
USE_ARM_ISA=y
RUBY=y
RUBY_PROTOCOL_MESI_THREE_LEVEL_HTM=y

9
build_opts/ARM_MOESI_hammer
View File

@@ -1,5 +1,4 @@
# Copyright (c) 2019 ARM Limited
# All rights reserved.
USE_ARM_ISA = True
PROTOCOL = 'MOESI_hammer'
BUILD_ISA=y
USE_ARM_ISA=y
RUBY=y
RUBY_PROTOCOL_MOESI_HAMMER=y

10
build_opts/GCN3_X86
View File

@@ -1,4 +1,6 @@
PROTOCOL = 'GPU_VIPER'
USE_X86_ISA = True
TARGET_GPU_ISA = 'gcn3'
BUILD_GPU = True
RUBY=y
RUBY_PROTOCOL_GPU_VIPER=y
BUILD_ISA=y
USE_X86_ISA=y
GCN3_GPU_ISA=y
BUILD_GPU=y

4
build_opts/Garnet_standalone
View File

@@ -1,2 +1,2 @@
USE_NULL_ISA = True
PROTOCOL = 'Garnet_standalone'
RUBY=y
RUBY_PROTOCOL_GARNET_STANDALONE=y

6
build_opts/MIPS
View File

@@ -1,2 +1,4 @@
USE_MIPS_ISA = True
PROTOCOL = 'MI_example'
RUBY=y
RUBY_PROTOCOL_MI_EXAMPLE=y
BUILD_ISA=y
USE_MIPS_ISA=y

4
build_opts/NULL
View File

@@ -1,2 +1,2 @@
USE_NULL_ISA = True
PROTOCOL='MI_example'
RUBY=y
RUBY_PROTOCOL_MI_EXAMPLE=y

4
build_opts/NULL_MESI_Two_Level
View File

@@ -1,2 +1,2 @@
USE_NULL_ISA = True
PROTOCOL = 'MESI_Two_Level'
RUBY=y
RUBY_PROTOCOL_MESI_TWO_LEVEL=y

4
build_opts/NULL_MOESI_CMP_directory
View File

@@ -1,2 +1,2 @@
USE_NULL_ISA = True
PROTOCOL='MOESI_CMP_directory'
RUBY=y
RUBY_PROTOCOL_MOESI_CMP_DIRECTORY=y

4
build_opts/NULL_MOESI_CMP_token
View File

@@ -1,2 +1,2 @@
USE_NULL_ISA = True
PROTOCOL='MOESI_CMP_token'
RUBY=y
RUBY_PROTOCOL_MOESI_CMP_TOKEN=y

4
build_opts/NULL_MOESI_hammer
View File

@@ -1,2 +1,2 @@
USE_NULL_ISA = True
PROTOCOL='MOESI_hammer'
RUBY=y
RUBY_PROTOCOL_MOESI_HAMMER=y

6
build_opts/POWER
View File

@@ -1,2 +1,4 @@
USE_POWER_ISA = True
PROTOCOL = 'MI_example'
RUBY=y
RUBY_PROTOCOL_MI_EXAMPLE=y
BUILD_ISA=y
USE_POWER_ISA=y

6
build_opts/RISCV
View File

@@ -1,2 +1,4 @@
USE_RISCV_ISA = True
PROTOCOL = 'MI_example'
RUBY=y
RUBY_PROTOCOL_MI_EXAMPLE=y
BUILD_ISA=y
USE_RISCV_ISA=y

6
build_opts/SPARC
View File

@@ -1,2 +1,4 @@
USE_SPARC_ISA = True
PROTOCOL = 'MI_example'
RUBY=y
RUBY_PROTOCOL_MI_EXAMPLE=y
BUILD_ISA=y
USE_SPARC_ISA=y

10
build_opts/VEGA_X86
View File

@@ -1,4 +1,6 @@
PROTOCOL = 'GPU_VIPER'
USE_X86_ISA = True
TARGET_GPU_ISA = 'vega'
BUILD_GPU = True
RUBY=y
RUBY_PROTOCOL_GPU_VIPER=y
BUILD_ISA=y
USE_X86_ISA=y
VEGA_GPU_ISA=y
BUILD_GPU=y

8
build_opts/X86
View File

@@ -1,3 +1,5 @@
USE_X86_ISA = True
PROTOCOL = 'MESI_Two_Level'
NUMBER_BITS_PER_SET = '128'
RUBY=y
NUMBER_BITS_PER_SET=128
RUBY_PROTOCOL_MESI_TWO_LEVEL=y
BUILD_ISA=y
USE_X86_ISA=y

8
build_opts/X86_MESI_Two_Level
View File

@@ -1,3 +1,5 @@
USE_X86_ISA = True
PROTOCOL = 'MESI_Two_Level'
NUMBER_BITS_PER_SET = '128'
RUBY=y
NUMBER_BITS_PER_SET=128
RUBY_PROTOCOL_MESI_TWO_LEVEL=y
BUILD_ISA=y
USE_X86_ISA=y

6
build_opts/X86_MI_example
View File

@@ -1,2 +1,4 @@
USE_X86_ISA = True
PROTOCOL = 'MI_example'
RUBY=y
RUBY_PROTOCOL_MI_EXAMPLE=y
BUILD_ISA=y
USE_X86_ISA=y

6
build_opts/X86_MOESI_AMD_Base
View File

@@ -1,2 +1,4 @@
PROTOCOL = 'MOESI_AMD_Base'
USE_X86_ISA = True
RUBY=y
RUBY_PROTOCOL_MOESI_AMD_BASE=y
BUILD_ISA=y
USE_X86_ISA=y

14
build_tools/code_formatter.py
View File

@@ -46,7 +46,7 @@ import os
import re
class lookup(object):
class lookup:
def __init__(self, formatter, frame, *args, **kwargs):
self.frame = frame
self.formatter = formatter
@@ -106,7 +106,7 @@ class code_formatter_meta(type):
"""
def __init__(cls, name, bases, dct):
super(code_formatter_meta, cls).__init__(name, bases, dct)
super().__init__(name, bases, dct)
if "pattern" in dct:
pat = cls.pattern
else:
@@ -125,7 +125,7 @@ class code_formatter_meta(type):
cls.pattern = re.compile(pat, re.VERBOSE | re.DOTALL | re.MULTILINE)
class code_formatter(object, metaclass=code_formatter_meta):
class code_formatter(metaclass=code_formatter_meta):
delim = r"$"
ident = r"[_A-z]\w*"
pos = r"[0-9]+"
@@ -272,7 +272,7 @@ class code_formatter(object, metaclass=code_formatter_meta):
# check for a lone identifier
if ident:
indent = match.group("indent") # must be spaces
lone = "%s" % (l[ident],)
lone = f"{l[ident]}"
def indent_lines(gen):
for line in gen:
@@ -284,7 +284,7 @@ class code_formatter(object, metaclass=code_formatter_meta):
# check for an identifier, braced or not
ident = match.group("ident") or match.group("b_ident")
if ident is not None:
return "%s" % (l[ident],)
return f"{l[ident]}"
# check for a positional parameter, braced or not
pos = match.group("pos") or match.group("b_pos")
@@ -295,13 +295,13 @@ class code_formatter(object, metaclass=code_formatter_meta):
"Positional parameter #%d not found in pattern" % pos,
code_formatter.pattern,
)
return "%s" % (args[int(pos)],)
return f"{args[int(pos)]}"
# check for a double braced expression
eval_expr = match.group("eval")
if eval_expr is not None:
result = eval(eval_expr, {}, l)
return "%s" % (result,)
return f"{result}"
# check for an escaped delimiter
if match.group("escaped") is not None:

6
build_tools/cxx_config_cc.py
View File

@@ -3,6 +3,7 @@
# Copyright 2013 Mark D. Hill and David A. Wood
# Copyright 2017-2020 ARM Limited
# Copyright 2021 Google, Inc.
# Copyright 2023 COSEDA Technologies GmbH
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
@@ -42,7 +43,6 @@ import os.path
import sys
import importer
from code_formatter import code_formatter
parser = argparse.ArgumentParser()
@@ -58,8 +58,8 @@ importer.install()
module = importlib.import_module(args.modpath)
sim_object = getattr(module, sim_object_name)
from m5.params import isSimObjectClass
import m5.params
from m5.params import isSimObjectClass
code = code_formatter()
@@ -104,7 +104,7 @@ for param in sim_object._params.values():
for port in sim_object._ports.values():
is_vector = isinstance(port, m5.params.VectorPort)
is_requestor = port.role == "GEM5 REQUESTOR"
is_requestor = port.is_source
code(
'ports["%s"] = new PortDesc("%s", %s, %s);'

1
build_tools/cxx_config_hh.py
View File

@@ -42,7 +42,6 @@ import os.path
import sys
import importer
from code_formatter import code_formatter
parser = argparse.ArgumentParser()

2
build_tools/enum_cc.py
View File

@@ -42,7 +42,6 @@ import os.path
import sys
import importer
from code_formatter import code_formatter
parser = argparse.ArgumentParser()
@@ -118,7 +117,6 @@ code("} // namespace gem5")
if use_python:
name = enum.__name__
enum_name = enum.__name__ if enum.enum_name is None else enum.enum_name
wrapper_name = enum_name if enum.is_class else enum.wrapper_name

3
build_tools/enum_hh.py
View File

@@ -42,7 +42,6 @@ import os.path
import sys
import importer
from code_formatter import code_formatter
parser = argparse.ArgumentParser()
@@ -66,7 +65,7 @@ code = code_formatter()
wrapper_name = enum.wrapper_name
wrapper = "struct" if enum.wrapper_is_struct else "namespace"
name = enum.__name__ if enum.enum_name is None else enum.enum_name
idem_macro = "__ENUM__%s__%s__" % (wrapper_name, name)
idem_macro = f"__ENUM__{wrapper_name}__{name}__"
code(
"""\

8
build_tools/grammar.py
View File

@@ -36,7 +36,7 @@ class ParseError(Exception):
self.token = token
class Grammar(object):
class Grammar:
def setupLexerFactory(self, **kwargs):
if "module" in kwargs:
raise AttributeError("module is an illegal attribute")
@@ -92,7 +92,7 @@ class Grammar(object):
return self.current_lexer.lineno
raise AttributeError(
"'%s' object has no attribute '%s'" % (type(self), attr)
f"'{type(self)}' object has no attribute '{attr}'"
)
def parse_string(self, data, source="<string>", debug=None, tracking=0):
@@ -118,7 +118,7 @@ class Grammar(object):
def parse_file(self, f, **kwargs):
if isinstance(f, str):
source = f
f = open(f, "r")
f = open(f)
elif isinstance(f, file):
source = f.name
else:
@@ -137,7 +137,7 @@ class Grammar(object):
t.value,
)
else:
msg = "Syntax error at end of %s" % (self.current_source,)
msg = f"Syntax error at end of {self.current_source}"
raise ParseError(msg, t)
def t_error(self, t):

2
build_tools/infopy.py
View File

@@ -56,7 +56,7 @@ for source in args.files:
# `README.md = "..."` which is not valid as `md` is not a property of
# `README`.
src = os.path.basename(source).replace(".", "_")
with open(source, "r") as f:
with open(source) as f:
data = "".join(f)
code("${src} = ${{repr(data)}}")

55
build_tools/kconfig_base.py Executable file
View File

@@ -0,0 +1,55 @@
#! /usr/bin/env python3
#
# Copyright 2022 Google LLC
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import argparse
from code_formatter import code_formatter
parser = argparse.ArgumentParser()
parser.add_argument("output", help="path of generated base Kconfig file")
parser.add_argument("main", help="relative path to the main gem5 Kconfig file")
parser.add_argument("extras_dirs", nargs="*", help="EXTRAS paths")
args = parser.parse_args()
code = code_formatter()
code(
f"""# Automatically generated base Kconfig file, DO NOT EDIT!
source "{args.main}"
"""
)
for extras_dir in args.extras_dirs:
code(
f"""
osource "{extras_dir}/Kconfig"
"""
)
code.write(args.output)

2
build_tools/marshal.py
View File

@@ -74,7 +74,7 @@ if "LC_CTYPE" in os.environ:
_, cpp, python, modpath, abspath = sys.argv
with open(python, "r") as f:
with open(python) as f:
src = f.read()
compiled = compile(src, python, "exec")

2
build_tools/sim_object_param_struct_cc.py
View File

@@ -42,7 +42,6 @@ import os.path
import sys
import importer
from code_formatter import code_formatter
parser = argparse.ArgumentParser()
@@ -88,7 +87,6 @@ ports = sim_object._ports.local
# only include pybind if python is enabled in the build
if use_python:
code(
"""#include "pybind11/pybind11.h"
#include "pybind11/stl.h"

3
build_tools/sim_object_param_struct_hh.py
View File

@@ -42,7 +42,6 @@ import os.path
import sys
import importer
from code_formatter import code_formatter
parser = argparse.ArgumentParser()
@@ -81,7 +80,7 @@ except:
warned_about_nested_templates = False
class CxxClass(object):
class CxxClass:
def __init__(self, sig, template_params=[]):
# Split the signature into its constituent parts. This could
# potentially be done with regular expressions, but

8
configs/common/Benchmarks.py
View File

@@ -24,8 +24,14 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from common.SysPaths import script, disk, binary
from os import environ as env
from common.SysPaths import (
binary,
disk,
script,
)
from m5.defines import buildEnv

29
configs/common/CacheConfig.py
View File

@@ -40,13 +40,13 @@
# Configure the M5 cache hierarchy config in one place
#
from common import ObjectList
from common.Caches import *
import m5
from m5.objects import *
from gem5.isas import ISA
from gem5.runtime import get_runtime_isa
from common.Caches import *
from common import ObjectList
from gem5.isas import ISA
def _get_hwp(hwp_option):
@@ -117,9 +117,6 @@ def config_cache(options, system):
None,
)
if get_runtime_isa() in [ISA.X86, ISA.RISCV]:
walk_cache_class = PageTableWalkerCache
# Set the cache line size of the system
system.cache_line_size = options.cacheline_size
@@ -150,11 +147,13 @@ def config_cache(options, system):
icache = icache_class(**_get_cache_opts("l1i", options))
dcache = dcache_class(**_get_cache_opts("l1d", options))
# If we have a walker cache specified, instantiate two
# instances here
if walk_cache_class:
iwalkcache = walk_cache_class()
dwalkcache = walk_cache_class()
# If we are using ISA.X86 or ISA.RISCV, we set walker caches.
if ObjectList.cpu_list.get_isa(options.cpu_type) in [
ISA.RISCV,
ISA.X86,
]:
iwalkcache = PageTableWalkerCache()
dwalkcache = PageTableWalkerCache()
else:
iwalkcache = None
dwalkcache = None
@@ -192,7 +191,11 @@ def config_cache(options, system):
# on these names. For simplicity, we would advise configuring
# it to use this naming scheme; if this isn't possible, change
# the names below.
if get_runtime_isa() in [ISA.X86, ISA.ARM, ISA.RISCV]:
if ObjectList.cpu_list.get_isa(options.cpu_type) in [
ISA.X86,
ISA.ARM,
ISA.RISCV,
]:
system.cpu[i].addPrivateSplitL1Caches(
ExternalCache("cpu%d.icache" % i),
ExternalCache("cpu%d.dcache" % i),

11
configs/common/Caches.py
View File

@@ -39,8 +39,8 @@
from m5.defines import buildEnv
from m5.objects import *
from gem5.isas import ISA
from gem5.runtime import get_runtime_isa
# Base implementations of L1, L2, IO and TLB-walker caches. There are
# used in the regressions and also as base components in the
@@ -96,11 +96,4 @@ class PageTableWalkerCache(Cache):
mshrs = 10
size = "1kB"
tgts_per_mshr = 12
# the x86 table walker actually writes to the table-walker cache
if get_runtime_isa() in [ISA.X86, ISA.RISCV]:
is_read_only = False
else:
is_read_only = True
# Writeback clean lines as well
writeback_clean = True
is_read_only = False

13
configs/common/CpuConfig.py
View File

@@ -33,8 +33,19 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5 import fatal
import m5.objects
from m5 import fatal
from gem5.isas import ISA
isa_string_map = {
ISA.X86: "X86",
ISA.ARM: "Arm",
ISA.RISCV: "Riscv",
ISA.SPARC: "Sparc",
ISA.POWER: "Power",
ISA.MIPS: "Mips",
}
def config_etrace(cpu_cls, cpu_list, options):

5
configs/common/FSConfig.py
View File

@@ -38,12 +38,13 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from common import ObjectList
from common.Benchmarks import *
import m5
import m5.defines
from m5.objects import *
from m5.util import *
from common.Benchmarks import *
from common import ObjectList
# Populate to reflect supported os types per target ISA
os_types = set()

29
configs/common/FileSystemConfig.py
View File

@@ -36,18 +36,31 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import getpass
import operator
import os
import platform
from functools import reduce
from os import (
access,
getpid,
listdir,
makedirs,
mkdir,
stat,
)
from os.path import isdir
from os.path import join as joinpath
from pwd import getpwuid
from shutil import (
copyfile,
rmtree,
)
import m5
from m5.objects import *
from m5.util.convert import *
from functools import reduce
import operator, os, platform, getpass
from os import mkdir, makedirs, getpid, listdir, stat, access
from pwd import getpwuid
from os.path import join as joinpath
from os.path import isdir
from shutil import rmtree, copyfile
def hex_mask(terms):
dec_mask = reduce(operator.or_, [2**i for i in terms], 0)

2
configs/common/GPUTLBConfig.py
View File

@@ -36,7 +36,6 @@ from m5.objects import *
def TLB_constructor(options, level, gpu_ctrl=None, full_system=False):
if full_system:
constructor_call = (
"VegaGPUTLB(\
@@ -71,7 +70,6 @@ def TLB_constructor(options, level, gpu_ctrl=None, full_system=False):
def Coalescer_constructor(options, level, full_system):
if full_system:
constructor_call = (
"VegaTLBCoalescer(probesPerCycle = \

1
configs/common/GPUTLBOptions.py
View File

@@ -29,7 +29,6 @@
def tlb_options(parser):
# ===================================================================
# TLB Configuration
# ===================================================================

2
configs/common/HMC.py
View File

@@ -430,7 +430,6 @@ def add_options(parser):
# configure HMC host controller
def config_hmc_host_ctrl(opt, system):
# create HMC host controller
system.hmc_host = SubSystem()
@@ -533,7 +532,6 @@ def config_hmc_host_ctrl(opt, system):
# Create an HMC device
def config_hmc_dev(opt, system, hmc_host):
# create HMC device
system.hmc_dev = SubSystem()

10
configs/common/MemConfig.py
View File

@@ -33,14 +33,17 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from common import (
HMC,
ObjectList,
)
import m5.objects
from common import ObjectList
from common import HMC
def create_mem_intf(intf, r, i, intlv_bits, intlv_size, xor_low_bit):
"""
Helper function for creating a single memoy controller from the given
Helper function for creating a single memory controller from the given
options. This function is invoked multiple times in config_mem function
to create an array of controllers.
"""
@@ -174,6 +177,7 @@ def config_mem(options, system):
nbr_mem_ctrls = opt_mem_channels
import math
from m5.util import fatal
intlv_bits = int(math.log(nbr_mem_ctrls, 2))

41
configs/common/ObjectList.py
View File

@@ -34,15 +34,18 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from gem5.runtime import get_supported_isas
import m5.objects
import m5.internal.params
import inspect
import sys
from textwrap import TextWrapper
import m5.internal.params
import m5.objects
class ObjectList(object):
from gem5.isas import ISA
from gem5.runtime import get_supported_isas
class ObjectList:
"""Creates a list of objects that are sub-classes of a given class."""
def _is_obj_class(self, cls):
@@ -86,7 +89,7 @@ class ObjectList(object):
print(line)
if self._aliases:
print("\Aliases:")
print(r"\Aliases:")
for alias, target in list(self._aliases.items()):
print(f"\t{alias} => {target}")
@@ -127,14 +130,14 @@ class CPUList(ObjectList):
# We can't use the normal inspect.isclass because the ParamFactory
# and ProxyFactory classes have a tendency to confuse it.
try:
return super(CPUList, self)._is_obj_class(cls) and not issubclass(
return super()._is_obj_class(cls) and not issubclass(
cls, m5.objects.CheckerCPU
)
except (TypeError, AttributeError):
return False
def _add_objects(self):
super(CPUList, self)._add_objects()
super()._add_objects()
from importlib import import_module
@@ -157,6 +160,27 @@ class CPUList(ObjectList):
):
self._sub_classes[name] = cls
def get_isa(self, name: str) -> ISA:
"""For a given CPU (string representation) determine the ISA of the
CPU."""
cls = self.get(name)
if hasattr(m5.objects, "X86CPU") and issubclass(
cls, m5.objects.X86CPU
):
return ISA.X86
elif hasattr(m5.objects, "ArmCPU") and issubclass(
cls, m5.objects.ArmCPU
):
return ISA.ARM
elif hasattr(m5.objects, "RiscvCPU") and issubclass(
cls, m5.objects.RiscvCPU
):
return ISA.RISCV
else:
raise ValueError("Unable to determine CPU ISA.")
class EnumList(ObjectList):
"""Creates a list of possible values for a given enum class."""
@@ -164,7 +188,7 @@ class EnumList(ObjectList):
def _add_objects(self):
"""Add all enum values to the ObjectList"""
self._sub_classes = {}
for (key, value) in list(self.base_cls.__members__.items()):
for key, value in list(self.base_cls.__members__.items()):
# All Enums have a value Num_NAME at the end which we
# do not want to include
if not key.startswith("Num_"):
@@ -204,3 +228,4 @@ def _subclass_tester(name):
is_kvm_cpu = _subclass_tester("BaseKvmCPU")
is_noncaching_cpu = _subclass_tester("NonCachingSimpleCPU")
is_o3_cpu = _subclass_tester("BaseO3CPU")

38
configs/common/Options.py
View File

@@ -37,13 +37,20 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import argparse
from typing import Optional
from common import (
CpuConfig,
ObjectList,
)
from common.Benchmarks import *
import m5
from m5.defines import buildEnv
from m5.objects import *
from common.Benchmarks import *
from common import ObjectList
from gem5.isas import ISA
from gem5.runtime import get_supported_isas
vio_9p_help = """\
Enable the Virtio 9P device and set the path to share. The default 9p path is
@@ -237,9 +244,13 @@ def addNoISAOptions(parser):
# Add common options that assume a non-NULL ISA.
def addCommonOptions(parser):
def addCommonOptions(parser, default_isa: Optional[ISA] = None):
# start by adding the base options that do not assume an ISA
addNoISAOptions(parser)
if default_isa is None:
isa = list(get_supported_isas())[0]
else:
isa = default_isa
# system options
parser.add_argument(
@@ -250,7 +261,7 @@ def addCommonOptions(parser):
)
parser.add_argument(
"--cpu-type",
default="AtomicSimpleCPU",
default=CpuConfig.isa_string_map[isa] + "AtomicSimpleCPU",
choices=ObjectList.cpu_list.get_names(),
help="type of cpu to run with",
)
@@ -581,7 +592,7 @@ def addCommonOptions(parser):
parser.add_argument(
"--restore-with-cpu",
action="store",
default="AtomicSimpleCPU",
default=CpuConfig.isa_string_map[isa] + "AtomicSimpleCPU",
choices=ObjectList.cpu_list.get_names(),
help="cpu type for restoring from a checkpoint",
)
@@ -784,12 +795,20 @@ def addFSOptions(parser):
"files in the gem5 output directory",
)
if buildEnv["USE_ARM_ISA"]:
if buildEnv["USE_ARM_ISA"] or buildEnv["USE_RISCV_ISA"]:
parser.add_argument(
"--bare-metal",
action="store_true",
help="Provide the raw system without the linux specific bits",
)
parser.add_argument(
"--dtb-filename",
action="store",
type=str,
help="Specifies device tree blob file to use with device-tree-"
"enabled kernels",
)
if buildEnv["USE_ARM_ISA"]:
parser.add_argument(
"--list-machine-types",
action=ListPlatform,
@@ -802,13 +821,6 @@ def addFSOptions(parser):
choices=ObjectList.platform_list.get_names(),
default="VExpress_GEM5_V1",
)
parser.add_argument(
"--dtb-filename",
action="store",
type=str,
help="Specifies device tree blob file to use with device-tree-"
"enabled kernels",
)
parser.add_argument(
"--enable-context-switch-stats-dump",
action="store_true",

7
configs/common/SimpleOpts.py
View File

@@ -1,4 +1,3 @@
# -*- coding: utf-8 -*-
# Copyright (c) 2015 Jason Power
# All rights reserved.
#
@@ -35,12 +34,12 @@ from each class instead of only from the configuration script.
# Module-level variable to track if we've called the parse_args function yet
called_parse_args = False
# For fatal
import m5
# import the argument parser
from argparse import ArgumentParser
# For fatal
import m5
# add the args we want to be able to control from the command line
parser = ArgumentParser()

29
configs/common/Simulation.py
View File

@@ -41,8 +41,10 @@ import sys
from os import getcwd
from os.path import join as joinpath
from common import CpuConfig
from common import ObjectList
from common import (
CpuConfig,
ObjectList,
)
import m5
from m5.defines import buildEnv
@@ -79,7 +81,10 @@ def setCPUClass(options):
TmpClass, test_mem_mode = getCPUClass(options.restore_with_cpu)
elif options.fast_forward:
CPUClass = TmpClass
TmpClass = AtomicSimpleCPU
CPUISA = ObjectList.cpu_list.get_isa(options.cpu_type)
TmpClass = getCPUClass(
CpuConfig.isa_string_map[CPUISA] + "AtomicSimpleCPU"
)
test_mem_mode = "atomic"
# Ruby only supports atomic accesses in noncaching mode
@@ -128,9 +133,12 @@ def findCptDir(options, cptdir, testsys):
the appropriate directory.
"""
from os.path import isdir, exists
from os import listdir
import re
from os import listdir
from os.path import (
exists,
isdir,
)
if not isdir(cptdir):
fatal("checkpoint dir %s does not exist!", cptdir)
@@ -153,8 +161,8 @@ def findCptDir(options, cptdir, testsys):
# Assumes that the checkpoint dir names are formatted as follows:
dirs = listdir(cptdir)
expr = re.compile(
"cpt\.simpoint_(\d+)_inst_(\d+)"
+ "_weight_([\d\.e\-]+)_interval_(\d+)_warmup_(\d+)"
r"cpt\.simpoint_(\d+)_inst_(\d+)"
+ r"_weight_([\d\.e\-]+)_interval_(\d+)_warmup_(\d+)"
)
cpts = []
for dir in dirs:
@@ -190,7 +198,7 @@ def findCptDir(options, cptdir, testsys):
else:
dirs = listdir(cptdir)
expr = re.compile("cpt\.([0-9]+)")
expr = re.compile(r"cpt\.([0-9]+)")
cpts = []
for dir in dirs:
match = expr.match(dir)
@@ -325,7 +333,7 @@ def parseSimpointAnalysisFile(options, testsys):
line = simpoint_file.readline()
if not line:
break
m = re.match("(\d+)\s+(\d+)", line)
m = re.match(r"(\d+)\s+(\d+)", line)
if m:
interval = int(m.group(1))
else:
@@ -334,7 +342,7 @@ def parseSimpointAnalysisFile(options, testsys):
line = weight_file.readline()
if not line:
fatal("not enough lines in simpoint weight file!")
m = re.match("([0-9\.e\-]+)\s+(\d+)", line)
m = re.match(r"([0-9\.e\-]+)\s+(\d+)", line)
if m:
weight = float(m.group(1))
else:
@@ -771,7 +779,6 @@ def run(options, root, testsys, cpu_class):
if (
options.take_checkpoints or options.take_simpoint_checkpoints
) and options.checkpoint_restore:
if m5.options.outdir:
cptdir = m5.options.outdir
else:

9
configs/common/SysPaths.py
View File

@@ -24,13 +24,14 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import os, sys
import os
import sys
config_path = os.path.dirname(os.path.abspath(__file__))
config_root = os.path.dirname(config_path)
class PathSearchFunc(object):
class PathSearchFunc:
_sys_paths = None
environment_variable = "M5_PATH"
@@ -58,7 +59,7 @@ class PathSearchFunc(object):
paths = list(filter(os.path.isdir, paths))
if not paths:
raise IOError(
raise OSError(
"Can't find system files directory, "
"check your {} environment variable".format(
self.environment_variable
@@ -72,7 +73,7 @@ class PathSearchFunc(object):
try:
return next(p for p in paths if os.path.exists(p))
except StopIteration:
raise IOError(
raise OSError(
f"Can't find file '{filepath}' on {self.environment_variable}."
)

11
configs/common/cores/arm/HPI.py
View File

@@ -44,6 +44,7 @@ at: http://www.arm.com/ResearchEnablement/SystemModeling
from m5.objects import *
# Simple function to allow a string of [01x_] to be converted into a
# mask and value for use with MinorFUTiming
def make_implicant(implicant_string):
@@ -1679,7 +1680,14 @@ class HPI_MMU(ArmMMU):
dtb = ArmTLB(entry_type="data", size=256)
class HPI_BTB(SimpleBTB):
numEntries = 128
tagBits = 18
class HPI_BP(TournamentBP):
btb = HPI_BTB()
ras = ReturnAddrStack(numEntries=8)
localPredictorSize = 64
localCtrBits = 2
localHistoryTableSize = 64
@@ -1687,9 +1695,6 @@ class HPI_BP(TournamentBP):
globalCtrBits = 2
choicePredictorSize = 1024
choiceCtrBits = 2
BTBEntries = 128
BTBTagSize = 18
RASSize = 8
instShiftAmt = 2

42
tests/configs/memcheck.py → configs/common/cores/arm/O3_ARM_Etrace.py
View File

@@ -1,4 +1,4 @@
# Copyright (c) 2016 ARM Limited
# Copyright (c) 2012, 2017-2018, 2023 Arm Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -10,9 +10,6 @@
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2015 Jason Lowe-Power
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
@@ -36,25 +33,28 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import m5
from m5.objects import *
# the traffic generator is only available if we have protobuf support,
# so potentially skip this test
require_sim_object("TrafficGen")
# A wrapper around configs/example/memcheck.py
# For some reason, this is implicitly needed by run.py
root = None
from .O3_ARM_v7a import O3_ARM_v7a_3
def run_test(root):
# Called from tests/run.py
# O3_ARM_v7a_3 adapted to generate elastic traces
class O3_ARM_v7a_3_Etrace(O3_ARM_v7a_3):
# Make the number of entries in the ROB, LQ and SQ very
# large so that there are no stalls due to resource
# limitation as such stalls will get captured in the trace
# as compute delay. For replay, ROB, LQ and SQ sizes are
# modelled in the Trace CPU.
numROBEntries = 512
LQEntries = 128
SQEntries = 128
import sys
argv = [sys.argv[0], "-m %d" % maxtick]
# Execute the script we are wrapping
run_config("configs/example/memcheck.py", argv=argv)
def attach_probe_listener(self, inst_trace_file, data_trace_file):
# Attach the elastic trace probe listener. Set the protobuf trace
# file names. Set the dependency window size equal to the cpu it
# is attached to.
self.traceListener = m5.objects.ElasticTrace(
instFetchTraceFile=inst_trace_file,
dataDepTraceFile=data_trace_file,
depWindowSize=3 * self.numROBEntries,
)

14
configs/common/cores/arm/O3_ARM_v7a.py
View File

@@ -26,6 +26,7 @@
from m5.objects import *
# Simple ALU Instructions have a latency of 1
class O3_ARM_v7a_Simple_Int(FUDesc):
opList = [OpDesc(opClass="IntAlu", opLat=1)]
@@ -107,15 +108,19 @@ class O3_ARM_v7a_FUP(FUPool):
]
class O3_ARM_v7a_BTB(SimpleBTB):
numEntries = 2048
tagBits = 18
# Bi-Mode Branch Predictor
class O3_ARM_v7a_BP(BiModeBP):
btb = O3_ARM_v7a_BTB()
ras = ReturnAddrStack(numEntries=16)
globalPredictorSize = 8192
globalCtrBits = 2
choicePredictorSize = 8192
choiceCtrBits = 2
BTBEntries = 2048
BTBTagSize = 18
RASSize = 16
instShiftAmt = 2
@@ -202,9 +207,8 @@ class O3_ARM_v7aL2(Cache):
size = "1MB"
assoc = 16
write_buffers = 8
prefetch_on_access = True
clusivity = "mostly_excl"
# Simple stride prefetcher
prefetcher = StridePrefetcher(degree=8, latency=1)
prefetcher = StridePrefetcher(degree=8, latency=1, prefetch_on_access=True)
tags = BaseSetAssoc()
replacement_policy = RandomRP()

2
configs/common/cores/arm/__init__.py
View File

@@ -33,8 +33,8 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from pkgutil import iter_modules
from importlib import import_module
from pkgutil import iter_modules
_cpu_modules = [name for _, name, ispkg in iter_modules(__path__) if not ispkg]

4
configs/common/cores/arm/ex5_LITTLE.py
View File

@@ -31,6 +31,7 @@ from m5.objects import *
# ex5 LITTLE core (based on the ARM Cortex-A7)
# -----------------------------------------------------------------------
# Simple ALU Instructions have a latency of 3
class ex5_LITTLE_Simple_Int(MinorDefaultIntFU):
opList = [OpDesc(opClass="IntAlu", opLat=4)]
@@ -146,9 +147,8 @@ class L2(Cache):
size = "512kB"
assoc = 8
write_buffers = 16
prefetch_on_access = True
clusivity = "mostly_excl"
# Simple stride prefetcher
prefetcher = StridePrefetcher(degree=1, latency=1)
prefetcher = StridePrefetcher(degree=1, latency=1, prefetch_on_access=True)
tags = BaseSetAssoc()
replacement_policy = RandomRP()

14
configs/common/cores/arm/ex5_big.py
View File

@@ -31,6 +31,7 @@ from m5.objects import *
# ex5 big core (based on the ARM Cortex-A15)
# -----------------------------------------------------------------------
# Simple ALU Instructions have a latency of 1
class ex5_big_Simple_Int(FUDesc):
opList = [OpDesc(opClass="IntAlu", opLat=1)]
@@ -104,15 +105,19 @@ class ex5_big_FUP(FUPool):
]
class ex5_big_BTB(SimpleBTB):
numEntries = 4096
tagBits = 18
# Bi-Mode Branch Predictor
class ex5_big_BP(BiModeBP):
btb = ex5_big_BTB()
ras = ReturnAddrStack(numEntries=48)
globalPredictorSize = 4096
globalCtrBits = 2
choicePredictorSize = 1024
choiceCtrBits = 3
BTBEntries = 4096
BTBTagSize = 18
RASSize = 48
instShiftAmt = 2
@@ -195,9 +200,8 @@ class L2(Cache):
size = "2MB"
assoc = 16
write_buffers = 8
prefetch_on_access = True
clusivity = "mostly_excl"
# Simple stride prefetcher
prefetcher = StridePrefetcher(degree=8, latency=1)
prefetcher = StridePrefetcher(degree=8, latency=1, prefetch_on_access=True)
tags = BaseSetAssoc()
replacement_policy = RandomRP()

15
configs/common/cpu2000.py
View File

@@ -26,8 +26,15 @@
import os
import sys
from os.path import basename, exists, join as joinpath, normpath
from os.path import isdir, isfile, islink
from os.path import (
basename,
exists,
isdir,
isfile,
islink,
)
from os.path import join as joinpath
from os.path import normpath
spec_dist = os.environ.get("M5_CPU2000", "/dist/m5/cpu2000")
@@ -71,7 +78,7 @@ def copyfiles(srcdir, dstdir):
os.symlink(".", outlink)
class Benchmark(object):
class Benchmark:
def __init__(self, isa, os, input_set):
if not hasattr(self.__class__, "name"):
self.name = self.__class__.__name__
@@ -877,7 +884,7 @@ class vortex(Benchmark):
else:
raise AttributeError(f"unknown ISA {isa}")
super(vortex, self).__init__(isa, os, input_set)
super().__init__(isa, os, input_set)
def test(self, isa, os):
self.args = [f"{self.endian}.raw"]

37
configs/deprecated/example/fs.py
View File

@@ -45,25 +45,30 @@ import sys
import m5
from m5.defines import buildEnv
from m5.objects import *
from m5.util import addToPath, fatal, warn
from m5.util import (
addToPath,
fatal,
warn,
)
from m5.util.fdthelper import *
from gem5.isas import ISA
from gem5.runtime import get_runtime_isa
addToPath("../../")
from ruby import Ruby
from common import (
CacheConfig,
CpuConfig,
MemConfig,
ObjectList,
Options,
Simulation,
)
from common.Benchmarks import *
from common.Caches import *
from common.FSConfig import *
from common.SysPaths import *
from common.Benchmarks import *
from common import Simulation
from common import CacheConfig
from common import CpuConfig
from common import MemConfig
from common import ObjectList
from common.Caches import *
from common import Options
from ruby import Ruby
def cmd_line_template():
@@ -80,9 +85,8 @@ def cmd_line_template():
return None
def build_test_system(np):
def build_test_system(np, isa: ISA):
cmdline = cmd_line_template()
isa = get_runtime_isa()
if isa == ISA.MIPS:
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
elif isa == ISA.SPARC:
@@ -164,7 +168,7 @@ def build_test_system(np):
# assuming that there is just one such port.
test_sys.iobus.mem_side_ports = test_sys.ruby._io_port.in_ports
for (i, cpu) in enumerate(test_sys.cpu):
for i, cpu in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
@@ -378,7 +382,8 @@ else:
np = args.num_cpus
test_sys = build_test_system(np)
isa = ObjectList.cpu_list.get_isa(args.cpu_type)
test_sys = build_test_system(np, isa)
if len(bm) == 2:
drive_sys = build_drive_system(np)

38
configs/deprecated/example/se.py
View File

@@ -41,30 +41,35 @@
# "m5 test.py"
import argparse
import sys
import os
import sys
import m5
from m5.defines import buildEnv
from m5.objects import *
from m5.params import NULL
from m5.util import addToPath, fatal, warn
from m5.util import (
addToPath,
fatal,
warn,
)
from gem5.isas import ISA
from gem5.runtime import get_runtime_isa
addToPath("../../")
from ruby import Ruby
from common import Options
from common import Simulation
from common import CacheConfig
from common import CpuConfig
from common import ObjectList
from common import MemConfig
from common.FileSystemConfig import config_filesystem
from common import (
CacheConfig,
CpuConfig,
MemConfig,
ObjectList,
Options,
Simulation,
)
from common.Caches import *
from common.cpu2000 import *
from common.FileSystemConfig import config_filesystem
from ruby import Ruby
def get_processes(args):
@@ -94,7 +99,7 @@ def get_processes(args):
process.gid = os.getgid()
if args.env:
with open(args.env, "r") as f:
with open(args.env) as f:
process.env = [line.rstrip() for line in f]
if len(pargs) > idx:
@@ -113,7 +118,8 @@ def get_processes(args):
idx += 1
if args.smt:
assert args.cpu_type == "DerivO3CPU"
cpu_type = ObjectList.cpu_list.get(args.cpu_type)
assert ObjectList.is_o3_cpu(cpu_type), "SMT requires an O3CPU"
return multiprocesses, idx
else:
return multiprocesses, 1
@@ -144,7 +150,7 @@ if args.bench:
for app in apps:
try:
if get_runtime_isa() == ISA.ARM:
if ObjectList.cpu_list.get_isa(args.cpu_type) == ISA.ARM:
exec(
"workload = %s('arm_%s', 'linux', '%s')"
% (app, args.arm_iset, args.spec_input)
@@ -159,7 +165,7 @@ if args.bench:
multiprocesses.append(workload.makeProcess())
except:
print(
f"Unable to find workload for {get_runtime_isa().name()}: {app}",
f"Unable to find workload for ISA: {app}",
file=sys.stderr,
)
sys.exit(1)

2
configs/dist/sw.py vendored
View File

@@ -62,7 +62,7 @@ def build_switch(args):
for i in range(args.dist_size)
]
for (i, link) in enumerate(switch.portlink):
for i, link in enumerate(switch.portlink):
link.int0 = switch.interface[i]
return switch

15
configs/dram/lat_mem_rd.py
View File

@@ -33,18 +33,20 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import gzip
import argparse
import gzip
import os
import m5
from m5.objects import *
from m5.util import addToPath
from m5.stats import periodicStatDump
from m5.util import addToPath
addToPath("../")
from common import ObjectList
from common import MemConfig
from common import (
MemConfig,
ObjectList,
)
addToPath("../../util")
import protolib
@@ -150,6 +152,7 @@ cfg_file = open(cfg_file_name, "w")
burst_size = 64
system.cache_line_size = burst_size
# lazy version to check if an integer is a power of two
def is_pow2(num):
return num != 0 and ((num & (num - 1)) == 0)
@@ -177,13 +180,14 @@ iterations = 2
# do not pile up in the system, adjust if needed
itt = 150 * 1000
# for every data point, we create a trace containing a random address
# sequence, so that we can play back the same sequence for warming and
# the actual measurement
def create_trace(filename, max_addr, burst_size, itt):
try:
proto_out = gzip.open(filename, "wb")
except IOError:
except OSError:
print("Failed to open ", filename, " for writing")
exit(-1)
@@ -276,6 +280,7 @@ system.tgen.port = system.monitor.cpu_side_port
# basic to explore some of the options
from common.Caches import *
# a starting point for an L3 cache
class L3Cache(Cache):
assoc = 16

8
configs/dram/low_power_sweep.py
View File

@@ -37,13 +37,15 @@ import argparse
import m5
from m5.objects import *
from m5.util import addToPath
from m5.stats import periodicStatDump
from m5.util import addToPath
addToPath("../")
from common import ObjectList
from common import MemConfig
from common import (
MemConfig,
ObjectList,
)
# This script aims at triggering low power state transitions in the DRAM
# controller. The traffic generator is used in DRAM mode and traffic

10
configs/dram/sweep.py
View File

@@ -33,18 +33,20 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import math
import argparse
import math
import m5
from m5.objects import *
from m5.util import addToPath
from m5.stats import periodicStatDump
from m5.util import addToPath
addToPath("../")
from common import ObjectList
from common import MemConfig
from common import (
MemConfig,
ObjectList,
)
# this script is helpful to sweep the efficiency of a specific memory
# controller configuration, by varying the number of banks accessed,

60
configs/example/apu_se.py
View File

@@ -27,28 +27,32 @@
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
import argparse, os, re, getpass
import math
import argparse
import getpass
import glob
import inspect
import math
import os
import re
import m5
from m5.objects import *
from m5.util import addToPath
from gem5.isas import ISA
from gem5.runtime import get_runtime_isa
from gem5.runtime import get_supported_isas
addToPath("../")
from ruby import Ruby
from common import Options
from common import Simulation
from common import GPUTLBOptions, GPUTLBConfig
import hsaTopology
from common import FileSystemConfig
from common import (
FileSystemConfig,
GPUTLBConfig,
GPUTLBOptions,
Options,
Simulation,
)
from ruby import Ruby
# Adding script options
parser = argparse.ArgumentParser()
@@ -394,8 +398,8 @@ if buildEnv["PROTOCOL"] == "None":
fatal("GPU model requires ruby")
# Currently the gpu model requires only timing or detailed CPU
if not (args.cpu_type == "TimingSimpleCPU" or args.cpu_type == "DerivO3CPU"):
fatal("GPU model requires TimingSimpleCPU or DerivO3CPU")
if not (args.cpu_type == "X86TimingSimpleCPU" or args.cpu_type == "X86O3CPU"):
fatal("GPU model requires X86TimingSimpleCPU or X86O3CPU.")
# This file can support multiple compute units
assert args.num_compute_units >= 1
@@ -567,7 +571,7 @@ cp_list = []
cpu_list = []
CpuClass, mem_mode = Simulation.getCPUClass(args.cpu_type)
if CpuClass == AtomicSimpleCPU:
if CpuClass == X86AtomicSimpleCPU or CpuClass == AtomicSimpleCPU:
fatal("AtomicSimpleCPU is not supported")
if mem_mode != "timing":
fatal("Only the timing memory mode is supported")
@@ -673,6 +677,7 @@ gpu_driver.device = gpu_cmd_proc
shader.dispatcher = dispatcher
shader.gpu_cmd_proc = gpu_cmd_proc
# Create and assign the workload Check for rel_path in elements of
# base_list using test, returning the first full path that satisfies test
def find_path(base_list, rel_path, test):
@@ -698,7 +703,7 @@ if os.path.isdir(executable):
executable = find_file(benchmark_path, args.cmd)
if args.env:
with open(args.env, "r") as f:
with open(args.env) as f:
env = [line.rstrip() for line in f]
else:
env = [
@@ -756,7 +761,7 @@ if fast_forward:
]
# Other CPU strings cause bad addresses in ROCm. Revert back to M5 Simulator.
for (i, cpu) in enumerate(cpu_list):
for i, cpu in enumerate(cpu_list):
for j in range(len(cpu)):
cpu.isa[j].vendor_string = "M5 Simulator"
@@ -781,7 +786,7 @@ system.clk_domain = SrcClockDomain(
if fast_forward:
have_kvm_support = "BaseKvmCPU" in globals()
if have_kvm_support and get_runtime_isa() == ISA.X86:
if have_kvm_support and get_supported_isas().contains(ISA.X86):
system.vm = KvmVM()
system.m5ops_base = 0xFFFF0000
for i in range(len(host_cpu.workload)):
@@ -820,18 +825,15 @@ for i in range(args.num_cpus):
system.cpu[i].dcache_port = ruby_port.in_ports
ruby_port.mem_request_port = system.piobus.cpu_side_ports
if get_runtime_isa() == ISA.X86:
system.cpu[i].interrupts[0].pio = system.piobus.mem_side_ports
system.cpu[i].interrupts[
0
].int_requestor = system.piobus.cpu_side_ports
system.cpu[i].interrupts[
0
].int_responder = system.piobus.mem_side_ports
if fast_forward:
system.cpu[i].mmu.connectWalkerPorts(
ruby_port.in_ports, ruby_port.in_ports
)
# X86 ISA is implied from cpu type check above
system.cpu[i].interrupts[0].pio = system.piobus.mem_side_ports
system.cpu[i].interrupts[0].int_requestor = system.piobus.cpu_side_ports
system.cpu[i].interrupts[0].int_responder = system.piobus.mem_side_ports
if fast_forward:
system.cpu[i].mmu.connectWalkerPorts(
ruby_port.in_ports, ruby_port.in_ports
)
# attach CU ports to Ruby
# Because of the peculiarities of the CP core, you may have 1 CPU but 2

28
configs/example/arm/baremetal.py
View File

@@ -39,24 +39,29 @@ Research Starter Kit on System Modeling. More information can be found
at: http://www.arm.com/ResearchEnablement/SystemModeling
"""
import argparse
import os
import m5
from m5.util import addToPath
from m5.objects import *
from m5.options import *
from m5.util import addToPath
from gem5.simulate.exit_event import ExitEvent
import argparse
m5.util.addToPath("../..")
from common import SysPaths
from common import MemConfig
from common import ObjectList
from common.cores.arm import HPI
from common.cores.arm import O3_ARM_v7a
import devices
import workloads
from common import (
MemConfig,
ObjectList,
SysPaths,
)
from common.cores.arm import (
HPI,
O3_ARM_v7a,
)
# Pre-defined CPU configurations. Each tuple must be ordered as : (cpu_class,
# l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any of
@@ -171,9 +176,10 @@ def create(args):
system.workload = workload_class(object_file, system)
if args.with_pmu:
enabled_pmu_events = set(
(*args.pmu_dump_stats_on, *args.pmu_reset_stats_on)
)
enabled_pmu_events = {
*args.pmu_dump_stats_on,
*args.pmu_reset_stats_on,
}
exit_sim_on_control = bool(
enabled_pmu_events & set(pmu_control_events.keys())
)

133
configs/example/arm/devices.py
View File

@@ -39,8 +39,8 @@ import m5
from m5.objects import *
m5.util.addToPath("../../")
from common.Caches import *
from common import ObjectList
from common.Caches import *
have_kvm = "ArmV8KvmCPU" in ObjectList.cpu_list.get_names()
have_fastmodel = "FastModelCortexA76" in ObjectList.cpu_list.get_names()
@@ -338,56 +338,15 @@ class FastmodelCluster(CpuCluster):
pass
class BaseSimpleSystem(ArmSystem):
cache_line_size = 64
def __init__(self, mem_size, platform, **kwargs):
super(BaseSimpleSystem, self).__init__(**kwargs)
self.voltage_domain = VoltageDomain(voltage="1.0V")
self.clk_domain = SrcClockDomain(
clock="1GHz", voltage_domain=Parent.voltage_domain
)
if platform is None:
self.realview = VExpress_GEM5_V1()
else:
self.realview = platform
if hasattr(self.realview.gic, "cpu_addr"):
self.gic_cpu_addr = self.realview.gic.cpu_addr
self.terminal = Terminal()
self.vncserver = VncServer()
self.iobus = IOXBar()
# Device DMA -> MEM
self.mem_ranges = self.getMemRanges(int(Addr(mem_size)))
class ClusterSystem:
"""
Base class providing cpu clusters generation/handling methods to
SE/FS systems
"""
def __init__(self, **kwargs):
self._clusters = []
def getMemRanges(self, mem_size):
"""
Define system memory ranges. This depends on the physical
memory map provided by the realview platform and by the memory
size provided by the user (mem_size argument).
The method is iterating over all platform ranges until they cover
the entire user's memory requirements.
"""
mem_ranges = []
for mem_range in self.realview._mem_regions:
size_in_range = min(mem_size, mem_range.size())
mem_ranges.append(
AddrRange(start=mem_range.start, size=size_in_range)
)
mem_size -= size_in_range
if mem_size == 0:
return mem_ranges
raise ValueError("memory size too big for platform capabilities")
def numCpuClusters(self):
return len(self._clusters)
@@ -423,13 +382,87 @@ class BaseSimpleSystem(ArmSystem):
cluster.connectMemSide(cluster_mem_bus)
class SimpleSeSystem(System, ClusterSystem):
"""
Example system class for syscall emulation mode
"""
# Use a fixed cache line size of 64 bytes
cache_line_size = 64
def __init__(self, **kwargs):
System.__init__(self, **kwargs)
ClusterSystem.__init__(self, **kwargs)
# Create a voltage and clock domain for system components
self.voltage_domain = VoltageDomain(voltage="3.3V")
self.clk_domain = SrcClockDomain(
clock="1GHz", voltage_domain=self.voltage_domain
)
# Create the off-chip memory bus.
self.membus = SystemXBar()
def connect(self):
self.system_port = self.membus.cpu_side_ports
class BaseSimpleSystem(ArmSystem, ClusterSystem):
cache_line_size = 64
def __init__(self, mem_size, platform, **kwargs):
ArmSystem.__init__(self, **kwargs)
ClusterSystem.__init__(self, **kwargs)
self.voltage_domain = VoltageDomain(voltage="1.0V")
self.clk_domain = SrcClockDomain(
clock="1GHz", voltage_domain=Parent.voltage_domain
)
if platform is None:
self.realview = VExpress_GEM5_V1()
else:
self.realview = platform
if hasattr(self.realview.gic, "cpu_addr"):
self.gic_cpu_addr = self.realview.gic.cpu_addr
self.terminal = Terminal()
self.vncserver = VncServer()
self.iobus = IOXBar()
# Device DMA -> MEM
self.mem_ranges = self.getMemRanges(int(Addr(mem_size)))
def getMemRanges(self, mem_size):
"""
Define system memory ranges. This depends on the physical
memory map provided by the realview platform and by the memory
size provided by the user (mem_size argument).
The method is iterating over all platform ranges until they cover
the entire user's memory requirements.
"""
mem_ranges = []
for mem_range in self.realview._mem_regions:
size_in_range = min(mem_size, mem_range.size())
mem_ranges.append(
AddrRange(start=mem_range.start, size=size_in_range)
)
mem_size -= size_in_range
if mem_size == 0:
return mem_ranges
raise ValueError("memory size too big for platform capabilities")
class SimpleSystem(BaseSimpleSystem):
"""
Meant to be used with the classic memory model
"""
def __init__(self, caches, mem_size, platform=None, **kwargs):
super(SimpleSystem, self).__init__(mem_size, platform, **kwargs)
super().__init__(mem_size, platform, **kwargs)
self.membus = MemBus()
# CPUs->PIO
@@ -468,7 +501,7 @@ class ArmRubySystem(BaseSimpleSystem):
"""
def __init__(self, mem_size, platform=None, **kwargs):
super(ArmRubySystem, self).__init__(mem_size, platform, **kwargs)
super().__init__(mem_size, platform, **kwargs)
self._dma_ports = []
self._mem_ports = []

4
configs/example/arm/dist_bigLITTLE.py
View File

@@ -39,11 +39,11 @@
import argparse
import os
import fs_bigLITTLE as bL
import m5
from m5.objects import *
import fs_bigLITTLE as bL
m5.util.addToPath("../../dist")
import sw

191
configs/example/arm/etrace_se.py Normal file
View File

@@ -0,0 +1,191 @@
# Copyright (c) 2016-2017, 2022-2023 Arm Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import argparse
import os
import shlex
import m5
from m5.objects import *
from m5.util import addToPath
m5.util.addToPath("../..")
import devices
from common import ObjectList
def get_processes(cmd):
"""Interprets commands to run and returns a list of processes"""
cwd = os.getcwd()
multiprocesses = []
for idx, c in enumerate(cmd):
argv = shlex.split(c)
process = Process(pid=100 + idx, cwd=cwd, cmd=argv, executable=argv[0])
process.gid = os.getgid()
print("info: %d. command and arguments: %s" % (idx + 1, process.cmd))
multiprocesses.append(process)
return multiprocesses
def create(args):
"""Create and configure the system object."""
system = devices.SimpleSeSystem(
mem_mode="timing",
)
# Add CPUs to the system. A cluster of CPUs typically have
# private L1 caches and a shared L2 cache.
system.cpu_cluster = devices.ArmCpuCluster(
system,
args.num_cores,
args.cpu_freq,
"1.2V",
ObjectList.cpu_list.get("O3_ARM_v7a_3_Etrace"),
devices.L1I,
devices.L1D,
devices.L2,
)
# Attach the elastic trace probe listener to every CPU in the cluster
for cpu in system.cpu_cluster:
cpu.attach_probe_listener(args.inst_trace_file, args.data_trace_file)
# As elastic trace generation is enabled, make sure the memory system is
# minimal so that compute delays do not include memory access latencies.
# Configure the compulsory L1 caches for the O3CPU, do not configure
# any more caches.
system.addCaches(True, last_cache_level=1)
# For elastic trace, over-riding Simple Memory latency to 1ns."
system.memory = SimpleMemory(
range=AddrRange(start=0, size=args.mem_size),
latency="1ns",
port=system.membus.mem_side_ports,
)
# Parse the command line and get a list of Processes instances
# that we can pass to gem5.
processes = get_processes(args.commands_to_run)
if len(processes) != args.num_cores:
print(
"Error: Cannot map %d command(s) onto %d CPU(s)"
% (len(processes), args.num_cores)
)
sys.exit(1)
system.workload = SEWorkload.init_compatible(processes[0].executable)
# Assign one workload to each CPU
for cpu, workload in zip(system.cpu_cluster.cpus, processes):
cpu.workload = workload
return system
def main():
parser = argparse.ArgumentParser(epilog=__doc__)
parser.add_argument(
"commands_to_run",
metavar="command(s)",
nargs="+",
help="Command(s) to run",
)
parser.add_argument(
"--inst-trace-file",
action="store",
type=str,
help="""Instruction fetch trace file input to
Elastic Trace probe in a capture simulation and
Trace CPU in a replay simulation""",
default="fetchtrace.proto.gz",
)
parser.add_argument(
"--data-trace-file",
action="store",
type=str,
help="""Data dependency trace file input to
Elastic Trace probe in a capture simulation and
Trace CPU in a replay simulation""",
default="deptrace.proto.gz",
)
parser.add_argument("--cpu-freq", type=str, default="4GHz")
parser.add_argument(
"--num-cores", type=int, default=1, help="Number of CPU cores"
)
parser.add_argument(
"--mem-size",
action="store",
type=str,
default="2GB",
help="Specify the physical memory size",
)
args = parser.parse_args()
# Create a single root node for gem5's object hierarchy. There can
# only exist one root node in the simulator at any given
# time. Tell gem5 that we want to use syscall emulation mode
# instead of full system mode.
root = Root(full_system=False)
# Populate the root node with a system. A system corresponds to a
# single node with shared memory.
root.system = create(args)
# Instantiate the C++ object hierarchy. After this point,
# SimObjects can't be instantiated anymore.
m5.instantiate()
# Start the simulator. This gives control to the C++ world and
# starts the simulator. The returned event tells the simulation
# script why the simulator exited.
event = m5.simulate()
# Print the reason for the simulation exit. Some exit codes are
# requests for service (e.g., checkpoints) from the simulation
# script. We'll just ignore them here and exit.
print(f"{event.getCause()} ({event.getCode()}) @ {m5.curTick()}")
if __name__ == "__m5_main__":
main()

27
configs/example/arm/fs_bigLITTLE.py
View File

@@ -39,21 +39,29 @@
import argparse
import os
import sys
import m5
import m5.util
from m5.objects import *
m5.util.addToPath("../../")
from common import FSConfig
from common import SysPaths
from common import ObjectList
from common import Options
from common.cores.arm import ex5_big, ex5_LITTLE
import devices
from devices import AtomicCluster, KvmCluster, FastmodelCluster
from common import (
FSConfig,
ObjectList,
Options,
SysPaths,
)
from common.cores.arm import (
ex5_big,
ex5_LITTLE,
)
from devices import (
AtomicCluster,
FastmodelCluster,
KvmCluster,
)
default_disk = "aarch64-ubuntu-trusty-headless.img"
@@ -410,7 +418,8 @@ def build(options):
system.generateDtb(system.workload.dtb_filename)
if devices.have_fastmodel and issubclass(big_model, FastmodelCluster):
from m5 import arm_fast_model as fm, systemc as sc
from m5 import arm_fast_model as fm
from m5 import systemc as sc
# setup FastModels for simulation
fm.setup_simulation("cortexa76")

17
configs/example/arm/fs_power.py
View File

@@ -39,15 +39,18 @@
import argparse
import os
import m5
from m5.objects import MathExprPowerModel, PowerModel
import fs_bigLITTLE as bL
import m5
from m5.objects import (
MathExprPowerModel,
PowerModel,
)
class CpuPowerOn(MathExprPowerModel):
def __init__(self, cpu_path, **kwargs):
super(CpuPowerOn, self).__init__(**kwargs)
super().__init__(**kwargs)
# 2A per IPC, 3pA per cache miss
# and then convert to Watt
self.dyn = (
@@ -64,7 +67,7 @@ class CpuPowerOff(MathExprPowerModel):
class CpuPowerModel(PowerModel):
def __init__(self, cpu_path, **kwargs):
super(CpuPowerModel, self).__init__(**kwargs)
super().__init__(**kwargs)
self.pm = [
CpuPowerOn(cpu_path), # ON
CpuPowerOff(), # CLK_GATED
@@ -75,7 +78,7 @@ class CpuPowerModel(PowerModel):
class L2PowerOn(MathExprPowerModel):
def __init__(self, l2_path, **kwargs):
super(L2PowerOn, self).__init__(**kwargs)
super().__init__(**kwargs)
# Example to report l2 Cache overallAccesses
# The estimated power is converted to Watt and will vary based
# on the size of the cache
@@ -90,7 +93,7 @@ class L2PowerOff(MathExprPowerModel):
class L2PowerModel(PowerModel):
def __init__(self, l2_path, **kwargs):
super(L2PowerModel, self).__init__(**kwargs)
super().__init__(**kwargs)
# Choose a power model for every power state
self.pm = [
L2PowerOn(l2_path), # ON

24
configs/example/arm/ruby_fs.py
View File

@@ -33,24 +33,28 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import argparse
import os
import m5
from m5.util import addToPath
from m5.objects import *
from m5.options import *
import argparse
from m5.util import addToPath
m5.util.addToPath("../..")
from common import MemConfig
from common import ObjectList
from common import Options
from common import SysPaths
from common.cores.arm import O3_ARM_v7a, HPI
from ruby import Ruby
import devices
from common import (
MemConfig,
ObjectList,
Options,
SysPaths,
)
from common.cores.arm import (
HPI,
O3_ARM_v7a,
)
from ruby import Ruby
default_kernel = "vmlinux.arm64"
default_disk = "linaro-minimal-aarch64.img"

20
configs/example/arm/starter_fs.py
View File

@@ -38,22 +38,26 @@ Research Starter Kit on System Modeling. More information can be found
at: http://www.arm.com/ResearchEnablement/SystemModeling
"""
import argparse
import os
import m5
from m5.util import addToPath
from m5.objects import *
from m5.options import *
import argparse
from m5.util import addToPath
m5.util.addToPath("../..")
from common import SysPaths
from common import ObjectList
from common import MemConfig
from common.cores.arm import O3_ARM_v7a, HPI
import devices
from common import (
MemConfig,
ObjectList,
SysPaths,
)
from common.cores.arm import (
HPI,
O3_ARM_v7a,
)
default_kernel = "vmlinux.arm64"
default_disk = "linaro-minimal-aarch64.img"

114
configs/example/arm/starter_se.py
View File

@@ -38,21 +38,22 @@ Research Starter Kit on System Modeling. More information can be found
at: http://www.arm.com/ResearchEnablement/SystemModeling
"""
import os
import m5
from m5.util import addToPath
from m5.objects import *
import argparse
import os
import shlex
import m5
from m5.objects import *
from m5.util import addToPath
m5.util.addToPath("../..")
from common import ObjectList
from common import MemConfig
from common.cores.arm import HPI
import devices
from common import (
MemConfig,
ObjectList,
)
from common.cores.arm import HPI
# Pre-defined CPU configurations. Each tuple must be ordered as : (cpu_class,
# l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any of
@@ -64,72 +65,6 @@ cpu_types = {
}
class SimpleSeSystem(System):
"""
Example system class for syscall emulation mode
"""
# Use a fixed cache line size of 64 bytes
cache_line_size = 64
def __init__(self, args, **kwargs):
super(SimpleSeSystem, self).__init__(**kwargs)
# Setup book keeping to be able to use CpuClusters from the
# devices module.
self._clusters = []
self._num_cpus = 0
# Create a voltage and clock domain for system components
self.voltage_domain = VoltageDomain(voltage="3.3V")
self.clk_domain = SrcClockDomain(
clock="1GHz", voltage_domain=self.voltage_domain
)
# Create the off-chip memory bus.
self.membus = SystemXBar()
# Wire up the system port that gem5 uses to load the kernel
# and to perform debug accesses.
self.system_port = self.membus.cpu_side_ports
# Add CPUs to the system. A cluster of CPUs typically have
# private L1 caches and a shared L2 cache.
self.cpu_cluster = devices.ArmCpuCluster(
self,
args.num_cores,
args.cpu_freq,
"1.2V",
*cpu_types[args.cpu],
tarmac_gen=args.tarmac_gen,
tarmac_dest=args.tarmac_dest,
)
# Create a cache hierarchy (unless we are simulating a
# functional CPU in atomic memory mode) for the CPU cluster
# and connect it to the shared memory bus.
if self.cpu_cluster.memory_mode() == "timing":
self.cpu_cluster.addL1()
self.cpu_cluster.addL2(self.cpu_cluster.clk_domain)
self.cpu_cluster.connectMemSide(self.membus)
# Tell gem5 about the memory mode used by the CPUs we are
# simulating.
self.mem_mode = self.cpu_cluster.memory_mode()
def numCpuClusters(self):
return len(self._clusters)
def addCpuCluster(self, cpu_cluster):
assert cpu_cluster not in self._clusters
assert len(cpu_cluster) > 0
self._clusters.append(cpu_cluster)
self._num_cpus += len(cpu_cluster)
def numCpus(self):
return self._num_cpus
def get_processes(cmd):
"""Interprets commands to run and returns a list of processes"""
@@ -150,7 +85,31 @@ def get_processes(cmd):
def create(args):
"""Create and configure the system object."""
system = SimpleSeSystem(args)
cpu_class = cpu_types[args.cpu][0]
mem_mode = cpu_class.memory_mode()
# Only simulate caches when using a timing CPU (e.g., the HPI model)
want_caches = True if mem_mode == "timing" else False
system = devices.SimpleSeSystem(
mem_mode=mem_mode,
)
# Add CPUs to the system. A cluster of CPUs typically have
# private L1 caches and a shared L2 cache.
system.cpu_cluster = devices.ArmCpuCluster(
system,
args.num_cores,
args.cpu_freq,
"1.2V",
*cpu_types[args.cpu],
tarmac_gen=args.tarmac_gen,
tarmac_dest=args.tarmac_dest,
)
# Create a cache hierarchy for the cluster. We are assuming that
# clusters have core-private L1 caches and an L2 that's shared
# within the cluster.
system.addCaches(want_caches, last_cache_level=2)
# Tell components about the expected physical memory ranges. This
# is, for example, used by the MemConfig helper to determine where
@@ -160,6 +119,9 @@ def create(args):
# Configure the off-chip memory system.
MemConfig.config_mem(args, system)
# Wire up the system's memory system
system.connect()
# Parse the command line and get a list of Processes instances
# that we can pass to gem5.
processes = get_processes(args.commands_to_run)

14
configs/example/arm/workloads.py
View File

@@ -35,13 +35,17 @@
#
import inspect
from common.ObjectList import ObjectList
from common.SysPaths import (
binary,
disk,
)
import m5
from m5.objects import *
from m5.options import *
from common.ObjectList import ObjectList
from common.SysPaths import binary, disk
class ArmBaremetal(ArmFsWorkload):
"""Baremetal workload"""
@@ -49,7 +53,7 @@ class ArmBaremetal(ArmFsWorkload):
dtb_addr = 0
def __init__(self, obj, system, **kwargs):
super(ArmBaremetal, self).__init__(**kwargs)
super().__init__(**kwargs)
self.object_file = obj
@@ -76,7 +80,7 @@ class ArmTrustedFirmware(ArmFsWorkload):
dtb_addr = 0
def __init__(self, obj, system, **kwargs):
super(ArmTrustedFirmware, self).__init__(**kwargs)
super().__init__(**kwargs)
self.extras = [binary("bl1.bin"), binary("fip.bin")]
self.extras_addrs = [

6
configs/example/dramsys.py
View File

@@ -25,7 +25,6 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import m5
from m5.objects import *
traffic_gen = PyTrafficGen()
@@ -37,9 +36,8 @@ system.mem_mode = "timing"
system.cpu = traffic_gen
dramsys = DRAMSys(
configuration="ext/dramsys/DRAMSys/DRAMSys/"
"library/resources/simulations/ddr4-example.json",
resource_directory="ext/dramsys/DRAMSys/DRAMSys/library/resources",
configuration="ext/dramsys/DRAMSys/configs/ddr4-example.json",
resource_directory="ext/dramsys/DRAMSys/configs",
)
system.target = dramsys

80
configs/example/etrace_replay.py
View File

@@ -1,4 +1,4 @@
# Copyright (c) 2015 ARM Limited
# Copyright (c) 2015, 2023 Arm Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -37,16 +37,53 @@
import argparse
from m5.util import addToPath, fatal
from m5.util import (
addToPath,
fatal,
)
addToPath("../")
from common import Options
from common import Simulation
from common import CacheConfig
from common import MemConfig
from common import (
MemConfig,
Options,
Simulation,
)
from common.Caches import *
def config_cache(args, system):
"""
Configure the cache hierarchy. Only two configurations are natively
supported as an example: L1(I/D) only or L1 + L2.
"""
from common.CacheConfig import _get_cache_opts
system.l1i = L1_ICache(**_get_cache_opts("l1i", args))
system.l1d = L1_DCache(**_get_cache_opts("l1d", args))
system.cpu.dcache_port = system.l1d.cpu_side
system.cpu.icache_port = system.l1i.cpu_side
if args.l2cache:
# Provide a clock for the L2 and the L1-to-L2 bus here as they
# are not connected using addTwoLevelCacheHierarchy. Use the
# same clock as the CPUs.
system.l2 = L2Cache(
clk_domain=system.cpu_clk_domain, **_get_cache_opts("l2", args)
)
system.tol2bus = L2XBar(clk_domain=system.cpu_clk_domain)
system.l2.cpu_side = system.tol2bus.mem_side_ports
system.l2.mem_side = system.membus.cpu_side_ports
system.l1i.mem_side = system.tol2bus.cpu_side_ports
system.l1d.mem_side = system.tol2bus.cpu_side_ports
else:
system.l1i.mem_side = system.membus.cpu_side_ports
system.l1d.mem_side = system.membus.cpu_side_ports
parser = argparse.ArgumentParser()
Options.addCommonOptions(parser)
@@ -59,29 +96,18 @@ if "--ruby" in sys.argv:
args = parser.parse_args()
numThreads = 1
if args.cpu_type != "TraceCPU":
fatal(
"This is a script for elastic trace replay simulation, use "
"--cpu-type=TraceCPU\n"
)
if args.num_cpus > 1:
fatal("This script does not support multi-processor trace replay.\n")
# In this case FutureClass will be None as there is not fast forwarding or
# switching
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(args)
CPUClass.numThreads = numThreads
system = System(
cpu=CPUClass(cpu_id=0),
mem_mode=test_mem_mode,
mem_mode=TraceCPU.memory_mode(),
mem_ranges=[AddrRange(args.mem_size)],
cache_line_size=args.cacheline_size,
)
# Generate the TraceCPU
system.cpu = TraceCPU()
# Create a top-level voltage domain
system.voltage_domain = VoltageDomain(voltage=args.sys_voltage)
@@ -105,11 +131,6 @@ system.cpu_clk_domain = SrcClockDomain(
for cpu in system.cpu:
cpu.clk_domain = system.cpu_clk_domain
# BaseCPU no longer has default values for the BaseCPU.isa
# createThreads() is needed to fill in the cpu.isa
for cpu in system.cpu:
cpu.createThreads()
# Assign input trace files to the Trace CPU
system.cpu.instTraceFile = args.inst_trace_file
system.cpu.dataTraceFile = args.data_trace_file
@@ -118,8 +139,11 @@ system.cpu.dataTraceFile = args.data_trace_file
MemClass = Simulation.setMemClass(args)
system.membus = SystemXBar()
system.system_port = system.membus.cpu_side_ports
CacheConfig.config_cache(args, system)
# Configure the classic cache hierarchy
config_cache(args, system)
MemConfig.config_mem(args, system)
root = Root(full_system=False, system=system)
Simulation.run(args, root, system, FutureClass)
Simulation.run(args, root, system, None)

7
configs/example/garnet_synth_traffic.py
View File

@@ -26,11 +26,14 @@
#
# Author: Tushar Krishna
import argparse
import os
import sys
import m5
from m5.objects import *
from m5.defines import buildEnv
from m5.objects import *
from m5.util import addToPath
import os, argparse, sys
addToPath("../")

12
configs/example/gem5_library/arm-hello.py
View File

@@ -41,15 +41,15 @@ scons build/ARM/gem5.opt
```
"""
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import Resource
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
# This check ensures the gem5 binary is compiled to the ARM ISA target. If not,
# an exception will be thrown.
@@ -84,7 +84,7 @@ board.set_se_binary_workload(
# Any resource specified in this file will be automatically retrieved.
# At the time of writing, this file is a WIP and does not contain all
# resources. Jira ticket: https://gem5.atlassian.net/browse/GEM5-1096
Resource("arm-hello64-static")
obtain_resource("arm-hello64-static")
)
# Lastly we run the simulation.

18
configs/example/gem5_library/arm-ubuntu-run.py
View File

@@ -40,18 +40,20 @@ scons build/ARM/gem5.opt -j<NUM_CPUS>
"""
from gem5.isas import ISA
from m5.objects import ArmDefaultRelease
from gem5.utils.requires import requires
from gem5.resources.workload import Workload
from gem5.simulate.simulator import Simulator
from m5.objects import VExpress_GEM5_Foundation
from m5.objects import (
ArmDefaultRelease,
VExpress_GEM5_Foundation,
)
from gem5.coherence_protocol import CoherenceProtocol
from gem5.components.boards.arm_board import ArmBoard
from gem5.components.memory import DualChannelDDR4_2400
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
# This runs a check to ensure the gem5 binary is compiled for ARM and the
# protocol is CHI.
@@ -100,7 +102,7 @@ board = ArmBoard(
# Here we set a full system workload. The "arm64-ubuntu-20.04-boot" boots
# Ubuntu 20.04.
board.set_workload(Workload("arm64-ubuntu-20.04-boot"))
board.set_workload(obtain_resource("arm64-ubuntu-20.04-boot"))
# We define the system with the aforementioned system defined.

19
configs/example/gem5_library/caches/octopi-cache-example.py
View File

@@ -38,20 +38,23 @@ scons build/ARM_MESI_Three_Level/gem5.opt -j `nproc`
"""
from m5.objects import ArmDefaultRelease, VExpress_GEM5_Foundation
from m5.objects import (
ArmDefaultRelease,
VExpress_GEM5_Foundation,
)
from gem5.utils.requires import requires
from gem5.coherence_protocol import CoherenceProtocol
from gem5.components.boards.arm_board import ArmBoard
from gem5.components.memory import DualChannelDDR4_2400
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.cachehierarchies.ruby.caches.mesi_three_level.octopi import (
OctopiCache,
)
from gem5.components.memory import DualChannelDDR4_2400
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.coherence_protocol import CoherenceProtocol
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
from gem5.resources.workload import Workload
from gem5.utils.requires import requires
num_ccds = 1 # CCDs
num_cores_per_ccd = 8 # 8 cores/CCD
@@ -94,7 +97,7 @@ board = ArmBoard(
platform=platform,
)
board.set_workload(Workload("arm64-ubuntu-20.04-boot"))
board.set_workload(obtain_resource("arm64-ubuntu-20.04-boot"))
simulator = Simulator(board=board)
simulator.run()

14
configs/example/gem5_library/checkpoints/riscv-hello-restore-checkpoint.py
View File

@@ -46,15 +46,15 @@ scons build/RISCV/gem5.opt
```
"""
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import Resource
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
# This check ensures the gem5 binary is compiled to the RISCV ISA target.
# If not, an exception will be thrown.
@@ -89,8 +89,8 @@ board = SimpleBoard(
# configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py
board.set_se_binary_workload(
# the workload should be the same as the save-checkpoint script
Resource("riscv-hello"),
checkpoint=Resource("riscv-hello-example-checkpoint-v23"),
obtain_resource("riscv-hello"),
checkpoint=obtain_resource("riscv-hello-example-checkpoint"),
)
simulator = Simulator(

13
configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py
View File

@@ -44,15 +44,16 @@ scons build/RISCV/gem5.opt
"""
import argparse
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import Resource
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
parser = argparse.ArgumentParser()
@@ -101,7 +102,7 @@ board.set_se_binary_workload(
# Any resource specified in this file will be automatically retrieved.
# At the time of writing, this file is a WIP and does not contain all
# resources. Jira ticket: https://gem5.atlassian.net/browse/GEM5-1096
Resource("riscv-hello")
obtain_resource("riscv-hello")
)
# Lastly we run the simulation.

26
configs/example/gem5_library/checkpoints/simpoints-se-checkpoint.py
View File

@@ -48,22 +48,23 @@ scons build/X86/gem5.opt
"""
import argparse
from pathlib import Path
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.memory.single_channel import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import (
SimpointResource,
obtain_resource,
)
from gem5.resources.workload import Workload
from gem5.simulate.exit_event import ExitEvent
from gem5.simulate.exit_event_generators import save_checkpoint_generator
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.memory.single_channel import SingleChannelDDR3_1600
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.cpu_types import CPUTypes
from gem5.isas import ISA
from gem5.resources.workload import Workload
from gem5.resources.resource import obtain_resource, SimpointResource
from pathlib import Path
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.simulate.exit_event_generators import (
save_checkpoint_generator,
)
requires(isa_required=ISA.X86)
@@ -128,7 +129,6 @@ board.set_se_simpoint_workload(
)
dir = Path(args.checkpoint_path)
dir.mkdir(exist_ok=True)
simulator = Simulator(
board=board,

26
configs/example/gem5_library/checkpoints/simpoints-se-restore.py
View File

@@ -52,23 +52,29 @@ scons build/X86/gem5.opt
"""
from gem5.simulate.exit_event import ExitEvent
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
from pathlib import Path
from m5.stats import (
dump,
reset,
)
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
PrivateL1PrivateL2CacheHierarchy,
)
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.memory import DualChannelDDR4_2400
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import SimpointResource, obtain_resource
from gem5.resources.resource import (
SimpointResource,
obtain_resource,
)
from gem5.resources.workload import Workload
from gem5.resources.resource import SimpointResource
from pathlib import Path
from m5.stats import reset, dump
from gem5.simulate.exit_event import ExitEvent
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
requires(isa_required=ISA.X86)

12
configs/example/gem5_library/dramsys/arm-hello-dramsys.py
View File

@@ -33,17 +33,17 @@ DRRAMSys simulator. Please consult 'ext/dramsys/README' on how to compile
correctly. If this is not done correctly this script will run with error.
"""
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import Resource
from gem5.components.memory import DRAMSysDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.private_l1_cache_hierarchy import (
PrivateL1CacheHierarchy,
)
from gem5.components.memory import DRAMSysDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
# This check ensures the gem5 binary is compiled to the ARM ISA target. If not,
# an exception will be thrown.
@@ -78,7 +78,7 @@ board.set_se_binary_workload(
# Any resource specified in this file will be automatically retrieved.
# At the time of writing, this file is a WIP and does not contain all
# resources. Jira ticket: https://gem5.atlassian.net/browse/GEM5-1096
Resource("arm-hello64-static")
obtain_resource("arm-hello64-static")
)
# Lastly we run the simulation.

24
configs/example/gem5_library/dramsys/dramsys-traffic.py
View File

@@ -31,16 +31,14 @@ DRAMSys simulator.
DRRAMSys simulator. Please consult 'ext/dramsys/README' on how to compile
correctly. If this is not done correctly this script will run with error.
"""
import m5
from gem5.components.memory import DRAMSysMem
from gem5.components.boards.test_board import TestBoard
from gem5.components.memory.dramsys import DRAMSysMem
from gem5.components.processors.linear_generator import LinearGenerator
from m5.objects import Root
from gem5.simulate.simulator import Simulator
memory = DRAMSysMem(
configuration="ext/dramsys/DRAMSys/DRAMSys/"
"library/resources/simulations/ddr4-example.json",
resource_directory="ext/dramsys/DRAMSys/DRAMSys/library/resources",
configuration="ext/dramsys/DRAMSys/configs/ddr4-example.json",
recordable=True,
size="4GB",
)
@@ -51,12 +49,16 @@ generator = LinearGenerator(
num_cores=1,
max_addr=memory.get_size(),
)
board = TestBoard(
clk_freq="3GHz", generator=generator, memory=memory, cache_hierarchy=None
)
root = Root(full_system=False, system=board)
board._pre_instantiate()
m5.instantiate()
generator.start_traffic()
exit_event = m5.simulate()
simulator = Simulator(board=board)
simulator.run()
print(
"Exiting @ tick {} because {}.".format(
simulator.get_current_tick(), simulator.get_last_exit_event_cause()
)
)

28
configs/example/gem5_library/looppoints/create-looppoint-checkpoints.py
View File

@@ -47,22 +47,22 @@ scons build/X86/gem5.opt
```
"""
from gem5.simulate.exit_event import ExitEvent
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.memory.single_channel import SingleChannelDDR3_1600
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.cpu_types import CPUTypes
from gem5.isas import ISA
from gem5.resources.workload import Workload
import argparse
from pathlib import Path
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.memory.single_channel import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import obtain_resource
from gem5.simulate.exit_event import ExitEvent
from gem5.simulate.exit_event_generators import (
looppoint_save_checkpoint_generator,
)
import argparse
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
requires(isa_required=ISA.X86)
@@ -110,7 +110,9 @@ board = SimpleBoard(
cache_hierarchy=cache_hierarchy,
)
board.set_workload(Workload("x86-matrix-multiply-omp-100-8-looppoint-csv"))
board.set_workload(
obtain_resource("x86-matrix-multiply-omp-100-8-looppoint-csv")
)
dir = Path(args.checkpoint_path)
dir.mkdir(exist_ok=True)

20
configs/example/gem5_library/looppoints/restore-looppoint-checkpoint.py
View File

@@ -42,20 +42,23 @@ Usage
"""
import argparse
from gem5.simulate.exit_event import ExitEvent
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
from m5.stats import (
dump,
reset,
)
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
PrivateL1PrivateL2CacheHierarchy,
)
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.memory import DualChannelDDR4_2400
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import obtain_resource
from gem5.resources.workload import Workload
from m5.stats import reset, dump
from gem5.simulate.exit_event import ExitEvent
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
requires(isa_required=ISA.X86)
@@ -113,11 +116,12 @@ board = SimpleBoard(
)
board.set_workload(
Workload(
obtain_resource(
f"x86-matrix-multiply-omp-100-8-looppoint-region-{args.checkpoint_region}"
)
)
# This generator will dump the stats and exit the simulation loop when the
# simulation region reaches its end. In the case there is a warmup interval,
# the simulation stats are reset after the warmup is complete.

8
configs/example/gem5_library/memory_traffic.py
View File

@@ -36,14 +36,12 @@ and this channel is driven with 32GiB/s of traffic for 1ms.
import argparse
from m5.objects import MemorySize
from gem5.components.boards.test_board import TestBoard
from gem5.components.boards.test_board import TestBoard
from gem5.components.memory.dram_interfaces.hbm import HBM_2000_4H_1x64
from gem5.components.memory.hbm import HighBandwidthMemory
from gem5.components.processors.linear_generator import LinearGenerator
from gem5.components.processors.random_generator import RandomGenerator
from gem5.components.memory.hbm import HighBandwidthMemory
from gem5.components.memory.dram_interfaces.hbm import HBM_2000_4H_1x64
from gem5.simulate.simulator import Simulator

12
configs/example/gem5_library/power-hello.py
View File

@@ -41,15 +41,15 @@ scons build/POWER/gem5.opt
```
"""
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import Resource
from gem5.components.memory import SingleChannelDDR4_2400
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
from gem5.components.memory import SingleChannelDDR4_2400
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
# This check ensures the gem5 binary is compiled to the POWER ISA target.
# If not, an exception will be thrown.
@@ -75,7 +75,7 @@ board = SimpleBoard(
cache_hierarchy=cache_hierarchy,
)
board.set_se_binary_workload(Resource("power-hello"))
board.set_se_binary_workload(obtain_resource("power-hello"))
# Lastly we run the simulation.
simulator = Simulator(board=board)

12
configs/example/gem5_library/riscv-fs.py
View File

@@ -40,16 +40,16 @@ Characteristics
"""
from gem5.components.boards.riscv_board import RiscvBoard
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
PrivateL1PrivateL2CacheHierarchy,
)
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.utils.requires import requires
from gem5.resources.resource import Resource
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
# Run a check to ensure the right version of gem5 is being used.
requires(isa_required=ISA.RISCV)
@@ -79,8 +79,8 @@ board = RiscvBoard(
# Set the Full System workload.
board.set_kernel_disk_workload(
kernel=Resource("riscv-bootloader-vmlinux-5.10"),
disk_image=Resource("riscv-disk-img"),
kernel=obtain_resource("riscv-bootloader-vmlinux-5.10"),
disk_image=obtain_resource("riscv-disk-img"),
)
simulator = Simulator(board=board)

8
configs/example/gem5_library/riscv-ubuntu-run.py
View File

@@ -43,14 +43,14 @@ scons build/RISCV/gem5.opt
import m5
from m5.objects import Root
from gem5.utils.requires import requires
from gem5.components.boards.riscv_board import RiscvBoard
from gem5.components.memory import DualChannelDDR4_2400
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.isas import ISA
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
from gem5.resources.workload import Workload
from gem5.utils.requires import requires
# This runs a check to ensure the gem5 binary is compiled for RISCV.
@@ -88,7 +88,7 @@ board = RiscvBoard(
# Ubuntu 20.04. Once the system successfully boots it encounters an `m5_exit`
# instruction which stops the simulation. When the simulation has ended you may
# inspect `m5out/system.pc.com_1.device` to see the stdout.
board.set_workload(Workload("riscv-ubuntu-20.04-boot"))
board.set_workload(obtain_resource("riscv-ubuntu-20.04-boot"))
simulator = Simulator(board=board)
simulator.run()

14
configs/example/gem5_library/riscvmatched-fs.py
View File

@@ -38,14 +38,14 @@ scons build/RISCV/gem5.opt
```
"""
from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard
from gem5.utils.requires import requires
from gem5.isas import ISA
from gem5.simulate.simulator import Simulator
from gem5.resources.workload import Workload
import argparse
from gem5.isas import ISA
from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
requires(isa_required=ISA.RISCV)
parser = argparse.ArgumentParser(
@@ -76,7 +76,7 @@ board = RISCVMatchedBoard(
# In the case where the `-i` flag is passed, we add the kernel argument
# `init=/root/exit.sh`. This means the simulation will exit after the Linux
# Kernel has booted.
workload = Workload("riscv-ubuntu-20.04-boot")
workload = obtain_resource("riscv-ubuntu-20.04-boot")
kernel_args = board.get_default_kernel_args()
if args.to_init:
kernel_args.append("init=/root/exit.sh")

8
configs/example/gem5_library/riscvmatched-hello.py
View File

@@ -37,10 +37,10 @@ scons build/RISCV/gem5.opt
```
"""
from gem5.resources.resource import Resource
from gem5.simulate.simulator import Simulator
from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard
from gem5.isas import ISA
from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
requires(isa_required=ISA.RISCV)
@@ -49,7 +49,7 @@ requires(isa_required=ISA.RISCV)
board = RISCVMatchedBoard()
# set the hello world riscv binary as the board workload
board.set_se_binary_workload(Resource("riscv-hello"))
board.set_se_binary_workload(obtain_resource("riscv-hello"))
# run the simulation with the RISCV Matched board
simulator = Simulator(board=board, full_system=False)

80
configs/example/gem5_library/riscvmatched-microbenchmark-suite.py Normal file
View File

@@ -0,0 +1,80 @@
# Copyright (c) 2023 The Regents of the University of California
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
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"""
This script shows how to use a suite. In this example, we will use the
RISCVMatchedBoard and the RISCV Vertical Microbenchmark Suite,
and show the different functionalities of the suite.
The print statements in the script are for illustrative purposes only,
and are not required to run the script.
"""
from gem5.isas import ISA
from gem5.prebuilt.riscvmatched.riscvmatched_board import RISCVMatchedBoard
from gem5.resources.resource import obtain_resource
from gem5.simulate.simulator import Simulator
from gem5.utils.requires import requires
requires(isa_required=ISA.RISCV)
# instantiate the riscv matched board with default parameters
board = RISCVMatchedBoard()
# obtain the RISC-V Vertical Microbenchmarks
microbenchmarks = obtain_resource("riscv-vertical-microbenchmarks")
# list all the microbenchmarks present in the suite
print("Microbenchmarks present in the suite:")
print("====================================")
for workload in microbenchmarks:
print(f"Workload ID: {workload.get_id()}")
print(f"Workload Version: {workload.get_resource_version()}")
print(f"WorkloadResource Object: {workload}")
print("====================================")
# list all the WorkloadResource objects present in the suite
for resource in microbenchmarks:
print(f"WorkloadResource Object: {resource}")
# list all the available input groups in the suite
print("Input groups present in the suite:")
print(microbenchmarks.get_input_groups())
# for this example, we will filter the suite
# to run the Workload "riscv-cca-run"
# it has the input group 'cca', which is used as the filter
board.set_workload(list(microbenchmarks.with_input_group("cca"))[0])
# run the simulation with the RISCV Matched board
simulator = Simulator(board=board, full_system=False)
simulator.run()
print(
"Exiting @ tick {} because {}.".format(
simulator.get_current_tick(),
simulator.get_last_exit_event_cause(),
)
)

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