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configs: CHI inc transitions_per_cycle

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Previous limit may unintentionally throttle performance for controllers
with a large TBE table and high traffic.

Change-Id: I34d6f8727519b259bb3d4a80b1fff6c59197c508
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63672
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Tiago Mück
2021-04-13 20:16:34 -05:00
committed by Tiago Muck
parent eb5eab360f
commit ba3aa067a3
2 changed files with 4 additions and 3 deletions
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5
configs/ruby/CHI_config.py
View File

@@ -1,4 +1,4 @@
# Copyright (c) 2021 ARM Limited # Copyright (c) 2021,2022 ARM Limited
# All rights reserved. # All rights reserved.
# #
# The license below extends only to copyright in the software and shall # The license below extends only to copyright in the software and shall
@@ -206,7 +206,7 @@ class CHI_Cache_Controller(Cache_Controller):
# triggers. To limit the controller performance, tweak other # triggers. To limit the controller performance, tweak other
# params such as: input port buffer size, cache banks, and output # params such as: input port buffer size, cache banks, and output
# port latency # port latency
self.transitions_per_cycle = 128 self.transitions_per_cycle = 1024
# This should be set to true in the data cache controller to enable # This should be set to true in the data cache controller to enable
# timeouts on unique lines when a store conditional fails # timeouts on unique lines when a store conditional fails
self.sc_lock_enabled = False self.sc_lock_enabled = False
@@ -670,6 +670,7 @@ class CHI_SNF_Base(CHI_Node):
responseFromMemory=MessageBuffer(), responseFromMemory=MessageBuffer(),
requestToMemory=MessageBuffer(ordered=True), requestToMemory=MessageBuffer(ordered=True),
reqRdy=TriggerMessageBuffer(), reqRdy=TriggerMessageBuffer(),
transitions_per_cycle=1024,
) )
self.connectController(self._cntrl) self.connectController(self._cntrl)

2
src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py
View File

@@ -77,7 +77,7 @@ class AbstractNode(Cache_Controller):
# triggers. To limit the controller performance, tweak other # triggers. To limit the controller performance, tweak other
# params such as: input port buffer size, cache banks, and output # params such as: input port buffer size, cache banks, and output
# port latency # port latency
self.transitions_per_cycle = 128 self.transitions_per_cycle = 1024
# This should be set to true in the data cache controller to enable # This should be set to true in the data cache controller to enable
# timeouts on unique lines when a store conditional fails # timeouts on unique lines when a store conditional fails
self.sc_lock_enabled = False self.sc_lock_enabled = False