New directory structure:
- simulator source now in 'src' subdirectory
- imported files from 'ext' repository
- support building in arbitrary places, including
outside of the source tree. See comment at top
of SConstruct file for more details.
Regression tests are temporarily disabled; that
syetem needs more extensive revisions.
SConstruct:
Update for new directory structure.
Modify to support build trees that are not subdirectories
of the source tree. See comment at top of file for
more details.
Regression tests are temporarily disabled.
src/arch/SConscript:
src/arch/isa_parser.py:
src/python/SConscript:
Update for new directory structure.
--HG--
rename : build/SConstruct => SConstruct
rename : build/default_options/ALPHA_FS => build_opts/ALPHA_FS
rename : build/default_options/ALPHA_FS_TL => build_opts/ALPHA_FS_TL
rename : build/default_options/ALPHA_SE => build_opts/ALPHA_SE
rename : build/default_options/MIPS_SE => build_opts/MIPS_SE
rename : build/default_options/SPARC_SE => build_opts/SPARC_SE
rename : Doxyfile => src/Doxyfile
rename : SConscript => src/SConscript
rename : arch/SConscript => src/arch/SConscript
rename : arch/alpha/SConscript => src/arch/alpha/SConscript
rename : arch/alpha/aout_machdep.h => src/arch/alpha/aout_machdep.h
rename : arch/alpha/arguments.cc => src/arch/alpha/arguments.cc
rename : arch/alpha/arguments.hh => src/arch/alpha/arguments.hh
rename : arch/alpha/ecoff_machdep.h => src/arch/alpha/ecoff_machdep.h
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/ev5.hh => src/arch/alpha/ev5.hh
rename : arch/alpha/faults.cc => src/arch/alpha/faults.cc
rename : arch/alpha/faults.hh => src/arch/alpha/faults.hh
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/freebsd/system.hh => src/arch/alpha/freebsd/system.hh
rename : arch/alpha/isa/branch.isa => src/arch/alpha/isa/branch.isa
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/fp.isa => src/arch/alpha/isa/fp.isa
rename : arch/alpha/isa/int.isa => src/arch/alpha/isa/int.isa
rename : arch/alpha/isa/main.isa => src/arch/alpha/isa/main.isa
rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa
rename : arch/alpha/isa/opcdec.isa => src/arch/alpha/isa/opcdec.isa
rename : arch/alpha/isa/pal.isa => src/arch/alpha/isa/pal.isa
rename : arch/alpha/isa/unimp.isa => src/arch/alpha/isa/unimp.isa
rename : arch/alpha/isa/unknown.isa => src/arch/alpha/isa/unknown.isa
rename : arch/alpha/isa/util.isa => src/arch/alpha/isa/util.isa
rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh
rename : arch/alpha/linux/aligned.hh => src/arch/alpha/linux/aligned.hh
rename : arch/alpha/linux/hwrpb.hh => src/arch/alpha/linux/hwrpb.hh
rename : arch/alpha/linux/linux.cc => src/arch/alpha/linux/linux.cc
rename : arch/alpha/linux/linux.hh => src/arch/alpha/linux/linux.hh
rename : arch/alpha/linux/process.cc => src/arch/alpha/linux/process.cc
rename : arch/alpha/linux/process.hh => src/arch/alpha/linux/process.hh
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/linux/system.hh => src/arch/alpha/linux/system.hh
rename : arch/alpha/linux/thread_info.hh => src/arch/alpha/linux/thread_info.hh
rename : arch/alpha/linux/threadinfo.hh => src/arch/alpha/linux/threadinfo.hh
rename : arch/alpha/osfpal.cc => src/arch/alpha/osfpal.cc
rename : arch/alpha/osfpal.hh => src/arch/alpha/osfpal.hh
rename : arch/alpha/process.cc => src/arch/alpha/process.cc
rename : arch/alpha/process.hh => src/arch/alpha/process.hh
rename : arch/alpha/regfile.hh => src/arch/alpha/regfile.hh
rename : arch/alpha/stacktrace.cc => src/arch/alpha/stacktrace.cc
rename : arch/alpha/stacktrace.hh => src/arch/alpha/stacktrace.hh
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/system.hh => src/arch/alpha/system.hh
rename : arch/alpha/tlb.cc => src/arch/alpha/tlb.cc
rename : arch/alpha/tlb.hh => src/arch/alpha/tlb.hh
rename : arch/alpha/tru64/process.cc => src/arch/alpha/tru64/process.cc
rename : arch/alpha/tru64/process.hh => src/arch/alpha/tru64/process.hh
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : arch/alpha/tru64/system.hh => src/arch/alpha/tru64/system.hh
rename : arch/alpha/tru64/tru64.cc => src/arch/alpha/tru64/tru64.cc
rename : arch/alpha/tru64/tru64.hh => src/arch/alpha/tru64/tru64.hh
rename : arch/alpha/types.hh => src/arch/alpha/types.hh
rename : arch/alpha/utility.hh => src/arch/alpha/utility.hh
rename : arch/alpha/vtophys.cc => src/arch/alpha/vtophys.cc
rename : arch/alpha/vtophys.hh => src/arch/alpha/vtophys.hh
rename : arch/isa_parser.py => src/arch/isa_parser.py
rename : arch/isa_specific.hh => src/arch/isa_specific.hh
rename : arch/mips/SConscript => src/arch/mips/SConscript
rename : arch/mips/faults.cc => src/arch/mips/faults.cc
rename : arch/mips/faults.hh => src/arch/mips/faults.hh
rename : arch/mips/isa/base.isa => src/arch/mips/isa/base.isa
rename : arch/mips/isa/bitfields.isa => src/arch/mips/isa/bitfields.isa
rename : arch/mips/isa/decoder.isa => src/arch/mips/isa/decoder.isa
rename : arch/mips/isa/formats/basic.isa => src/arch/mips/isa/formats/basic.isa
rename : arch/mips/isa/formats/branch.isa => src/arch/mips/isa/formats/branch.isa
rename : arch/mips/isa/formats/formats.isa => src/arch/mips/isa/formats/formats.isa
rename : arch/mips/isa/formats/fp.isa => src/arch/mips/isa/formats/fp.isa
rename : arch/mips/isa/formats/int.isa => src/arch/mips/isa/formats/int.isa
rename : arch/mips/isa/formats/mem.isa => src/arch/mips/isa/formats/mem.isa
rename : arch/mips/isa/formats/noop.isa => src/arch/mips/isa/formats/noop.isa
rename : arch/mips/isa/formats/tlbop.isa => src/arch/mips/isa/formats/tlbop.isa
rename : arch/mips/isa/formats/trap.isa => src/arch/mips/isa/formats/trap.isa
rename : arch/mips/isa/formats/unimp.isa => src/arch/mips/isa/formats/unimp.isa
rename : arch/mips/isa/formats/unknown.isa => src/arch/mips/isa/formats/unknown.isa
rename : arch/mips/isa/formats/util.isa => src/arch/mips/isa/formats/util.isa
rename : arch/mips/isa/includes.isa => src/arch/mips/isa/includes.isa
rename : arch/mips/isa/main.isa => src/arch/mips/isa/main.isa
rename : arch/mips/isa/operands.isa => src/arch/mips/isa/operands.isa
rename : arch/mips/isa_traits.cc => src/arch/mips/isa_traits.cc
rename : arch/mips/isa_traits.hh => src/arch/mips/isa_traits.hh
rename : arch/mips/linux/linux.cc => src/arch/mips/linux/linux.cc
rename : arch/mips/linux/linux.hh => src/arch/mips/linux/linux.hh
rename : arch/mips/linux/process.cc => src/arch/mips/linux/process.cc
rename : arch/mips/linux/process.hh => src/arch/mips/linux/process.hh
rename : arch/mips/process.cc => src/arch/mips/process.cc
rename : arch/mips/process.hh => src/arch/mips/process.hh
rename : arch/mips/regfile/float_regfile.hh => src/arch/mips/regfile/float_regfile.hh
rename : arch/mips/regfile/int_regfile.hh => src/arch/mips/regfile/int_regfile.hh
rename : arch/mips/regfile/misc_regfile.hh => src/arch/mips/regfile/misc_regfile.hh
rename : arch/mips/regfile/regfile.hh => src/arch/mips/regfile/regfile.hh
rename : arch/mips/stacktrace.hh => src/arch/mips/stacktrace.hh
rename : arch/mips/types.hh => src/arch/mips/types.hh
rename : arch/mips/utility.hh => src/arch/mips/utility.hh
rename : arch/sparc/SConscript => src/arch/sparc/SConscript
rename : arch/sparc/faults.cc => src/arch/sparc/faults.cc
rename : arch/sparc/faults.hh => src/arch/sparc/faults.hh
rename : arch/sparc/isa/base.isa => src/arch/sparc/isa/base.isa
rename : arch/sparc/isa/bitfields.isa => src/arch/sparc/isa/bitfields.isa
rename : arch/sparc/isa/decoder.isa => src/arch/sparc/isa/decoder.isa
rename : arch/sparc/isa/formats.isa => src/arch/sparc/isa/formats.isa
rename : arch/sparc/isa/formats/basic.isa => src/arch/sparc/isa/formats/basic.isa
rename : arch/sparc/isa/formats/branch.isa => src/arch/sparc/isa/formats/branch.isa
rename : arch/sparc/isa/formats/integerop.isa => src/arch/sparc/isa/formats/integerop.isa
rename : arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem.isa
rename : arch/sparc/isa/formats/nop.isa => src/arch/sparc/isa/formats/nop.isa
rename : arch/sparc/isa/formats/priv.isa => src/arch/sparc/isa/formats/priv.isa
rename : arch/sparc/isa/formats/trap.isa => src/arch/sparc/isa/formats/trap.isa
rename : arch/sparc/isa/formats/unknown.isa => src/arch/sparc/isa/formats/unknown.isa
rename : arch/sparc/isa/includes.isa => src/arch/sparc/isa/includes.isa
rename : arch/sparc/isa/main.isa => src/arch/sparc/isa/main.isa
rename : arch/sparc/isa/operands.isa => src/arch/sparc/isa/operands.isa
rename : arch/sparc/isa_traits.hh => src/arch/sparc/isa_traits.hh
rename : arch/sparc/linux/linux.cc => src/arch/sparc/linux/linux.cc
rename : arch/sparc/linux/linux.hh => src/arch/sparc/linux/linux.hh
rename : arch/sparc/linux/process.cc => src/arch/sparc/linux/process.cc
rename : arch/sparc/linux/process.hh => src/arch/sparc/linux/process.hh
rename : arch/sparc/process.cc => src/arch/sparc/process.cc
rename : arch/sparc/process.hh => src/arch/sparc/process.hh
rename : arch/sparc/regfile.hh => src/arch/sparc/regfile.hh
rename : arch/sparc/solaris/process.cc => src/arch/sparc/solaris/process.cc
rename : arch/sparc/solaris/process.hh => src/arch/sparc/solaris/process.hh
rename : arch/sparc/solaris/solaris.cc => src/arch/sparc/solaris/solaris.cc
rename : arch/sparc/solaris/solaris.hh => src/arch/sparc/solaris/solaris.hh
rename : arch/sparc/stacktrace.hh => src/arch/sparc/stacktrace.hh
rename : arch/sparc/system.cc => src/arch/sparc/system.cc
rename : arch/sparc/system.hh => src/arch/sparc/system.hh
rename : arch/sparc/utility.hh => src/arch/sparc/utility.hh
rename : base/bitfield.hh => src/base/bitfield.hh
rename : base/callback.hh => src/base/callback.hh
rename : base/chunk_generator.hh => src/base/chunk_generator.hh
rename : base/circlebuf.cc => src/base/circlebuf.cc
rename : base/circlebuf.hh => src/base/circlebuf.hh
rename : base/compression/lzss_compression.cc => src/base/compression/lzss_compression.cc
rename : base/compression/lzss_compression.hh => src/base/compression/lzss_compression.hh
rename : base/compression/null_compression.hh => src/base/compression/null_compression.hh
rename : base/cprintf.cc => src/base/cprintf.cc
rename : base/cprintf.hh => src/base/cprintf.hh
rename : base/cprintf_formats.hh => src/base/cprintf_formats.hh
rename : base/crc.cc => src/base/crc.cc
rename : base/crc.hh => src/base/crc.hh
rename : base/date.cc => src/base/date.cc
rename : base/dbl_list.hh => src/base/dbl_list.hh
rename : base/endian.hh => src/base/endian.hh
rename : base/fast_alloc.cc => src/base/fast_alloc.cc
rename : base/fast_alloc.hh => src/base/fast_alloc.hh
rename : base/fenv.hh => src/base/fenv.hh
rename : base/fifo_buffer.cc => src/base/fifo_buffer.cc
rename : base/fifo_buffer.hh => src/base/fifo_buffer.hh
rename : base/hashmap.hh => src/base/hashmap.hh
rename : base/hostinfo.cc => src/base/hostinfo.cc
rename : base/hostinfo.hh => src/base/hostinfo.hh
rename : base/hybrid_pred.cc => src/base/hybrid_pred.cc
rename : base/hybrid_pred.hh => src/base/hybrid_pred.hh
rename : base/inet.cc => src/base/inet.cc
rename : base/inet.hh => src/base/inet.hh
rename : base/inifile.cc => src/base/inifile.cc
rename : base/inifile.hh => src/base/inifile.hh
rename : base/intmath.cc => src/base/intmath.cc
rename : base/intmath.hh => src/base/intmath.hh
rename : base/kgdb.h => src/base/kgdb.h
rename : base/loader/aout_object.cc => src/base/loader/aout_object.cc
rename : base/loader/aout_object.hh => src/base/loader/aout_object.hh
rename : base/loader/coff_sym.h => src/base/loader/coff_sym.h
rename : base/loader/coff_symconst.h => src/base/loader/coff_symconst.h
rename : base/loader/ecoff_object.cc => src/base/loader/ecoff_object.cc
rename : base/loader/ecoff_object.hh => src/base/loader/ecoff_object.hh
rename : base/loader/elf_object.cc => src/base/loader/elf_object.cc
rename : base/loader/elf_object.hh => src/base/loader/elf_object.hh
rename : base/loader/exec_aout.h => src/base/loader/exec_aout.h
rename : base/loader/exec_ecoff.h => src/base/loader/exec_ecoff.h
rename : base/loader/object_file.cc => src/base/loader/object_file.cc
rename : base/loader/object_file.hh => src/base/loader/object_file.hh
rename : base/loader/symtab.cc => src/base/loader/symtab.cc
rename : base/loader/symtab.hh => src/base/loader/symtab.hh
rename : base/match.cc => src/base/match.cc
rename : base/match.hh => src/base/match.hh
rename : base/misc.cc => src/base/misc.cc
rename : base/misc.hh => src/base/misc.hh
rename : base/mod_num.hh => src/base/mod_num.hh
rename : base/mysql.cc => src/base/mysql.cc
rename : base/mysql.hh => src/base/mysql.hh
rename : base/output.cc => src/base/output.cc
rename : base/output.hh => src/base/output.hh
rename : base/pollevent.cc => src/base/pollevent.cc
rename : base/pollevent.hh => src/base/pollevent.hh
rename : base/predictor.hh => src/base/predictor.hh
rename : base/random.cc => src/base/random.cc
rename : base/random.hh => src/base/random.hh
rename : base/range.cc => src/base/range.cc
rename : base/range.hh => src/base/range.hh
rename : base/refcnt.hh => src/base/refcnt.hh
rename : base/remote_gdb.cc => src/base/remote_gdb.cc
rename : base/remote_gdb.hh => src/base/remote_gdb.hh
rename : base/res_list.hh => src/base/res_list.hh
rename : base/sat_counter.cc => src/base/sat_counter.cc
rename : base/sat_counter.hh => src/base/sat_counter.hh
rename : base/sched_list.hh => src/base/sched_list.hh
rename : base/socket.cc => src/base/socket.cc
rename : base/socket.hh => src/base/socket.hh
rename : base/statistics.cc => src/base/statistics.cc
rename : base/statistics.hh => src/base/statistics.hh
rename : base/stats/events.cc => src/base/stats/events.cc
rename : base/stats/events.hh => src/base/stats/events.hh
rename : base/stats/flags.hh => src/base/stats/flags.hh
rename : base/stats/mysql.cc => src/base/stats/mysql.cc
rename : base/stats/mysql.hh => src/base/stats/mysql.hh
rename : base/stats/mysql_run.hh => src/base/stats/mysql_run.hh
rename : base/stats/output.hh => src/base/stats/output.hh
rename : base/stats/statdb.cc => src/base/stats/statdb.cc
rename : base/stats/statdb.hh => src/base/stats/statdb.hh
rename : base/stats/text.cc => src/base/stats/text.cc
rename : base/stats/text.hh => src/base/stats/text.hh
rename : base/stats/types.hh => src/base/stats/types.hh
rename : base/stats/visit.cc => src/base/stats/visit.cc
rename : base/stats/visit.hh => src/base/stats/visit.hh
rename : base/str.cc => src/base/str.cc
rename : base/str.hh => src/base/str.hh
rename : base/time.cc => src/base/time.cc
rename : base/time.hh => src/base/time.hh
rename : base/timebuf.hh => src/base/timebuf.hh
rename : base/trace.cc => src/base/trace.cc
rename : base/trace.hh => src/base/trace.hh
rename : base/traceflags.py => src/base/traceflags.py
rename : base/userinfo.cc => src/base/userinfo.cc
rename : base/userinfo.hh => src/base/userinfo.hh
rename : cpu/SConscript => src/cpu/SConscript
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.cc => src/cpu/base_dyn_inst.cc
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/cpu_exec_context.cc => src/cpu/cpu_exec_context.cc
rename : cpu/cpu_exec_context.hh => src/cpu/cpu_exec_context.hh
rename : cpu/cpu_models.py => src/cpu/cpu_models.py
rename : cpu/exec_context.hh => src/cpu/exec_context.hh
rename : cpu/exetrace.cc => src/cpu/exetrace.cc
rename : cpu/exetrace.hh => src/cpu/exetrace.hh
rename : cpu/inst_seq.hh => src/cpu/inst_seq.hh
rename : cpu/intr_control.cc => src/cpu/intr_control.cc
rename : cpu/intr_control.hh => src/cpu/intr_control.hh
rename : cpu/memtest/memtest.cc => src/cpu/memtest/memtest.cc
rename : cpu/memtest/memtest.hh => src/cpu/memtest/memtest.hh
rename : cpu/o3/2bit_local_pred.cc => src/cpu/o3/2bit_local_pred.cc
rename : cpu/o3/2bit_local_pred.hh => src/cpu/o3/2bit_local_pred.hh
rename : cpu/o3/alpha_cpu.cc => src/cpu/o3/alpha_cpu.cc
rename : cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha_cpu.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha_cpu_builder.cc
rename : cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha_cpu_impl.hh
rename : cpu/o3/alpha_dyn_inst.cc => src/cpu/o3/alpha_dyn_inst.cc
rename : cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha_dyn_inst.hh
rename : cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/o3/alpha_impl.hh => src/cpu/o3/alpha_impl.hh
rename : cpu/o3/alpha_params.hh => src/cpu/o3/alpha_params.hh
rename : cpu/o3/bpred_unit.cc => src/cpu/o3/bpred_unit.cc
rename : cpu/o3/bpred_unit.hh => src/cpu/o3/bpred_unit.hh
rename : cpu/o3/bpred_unit_impl.hh => src/cpu/o3/bpred_unit_impl.hh
rename : cpu/o3/btb.cc => src/cpu/o3/btb.cc
rename : cpu/o3/btb.hh => src/cpu/o3/btb.hh
rename : cpu/o3/comm.hh => src/cpu/o3/comm.hh
rename : cpu/o3/commit.cc => src/cpu/o3/commit.cc
rename : cpu/o3/commit.hh => src/cpu/o3/commit.hh
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/cpu.hh => src/cpu/o3/cpu.hh
rename : cpu/o3/cpu_policy.hh => src/cpu/o3/cpu_policy.hh
rename : cpu/o3/decode.cc => src/cpu/o3/decode.cc
rename : cpu/o3/decode.hh => src/cpu/o3/decode.hh
rename : cpu/o3/decode_impl.hh => src/cpu/o3/decode_impl.hh
rename : cpu/o3/fetch.cc => src/cpu/o3/fetch.cc
rename : cpu/o3/fetch.hh => src/cpu/o3/fetch.hh
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/free_list.cc => src/cpu/o3/free_list.cc
rename : cpu/o3/free_list.hh => src/cpu/o3/free_list.hh
rename : cpu/o3/iew.cc => src/cpu/o3/iew.cc
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.cc => src/cpu/o3/inst_queue.cc
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/mem_dep_unit.cc => src/cpu/o3/mem_dep_unit.cc
rename : cpu/o3/mem_dep_unit.hh => src/cpu/o3/mem_dep_unit.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/ras.cc => src/cpu/o3/ras.cc
rename : cpu/o3/ras.hh => src/cpu/o3/ras.hh
rename : cpu/o3/regfile.hh => src/cpu/o3/regfile.hh
rename : cpu/o3/rename.cc => src/cpu/o3/rename.cc
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/rename_map.cc => src/cpu/o3/rename_map.cc
rename : cpu/o3/rename_map.hh => src/cpu/o3/rename_map.hh
rename : cpu/o3/rob.cc => src/cpu/o3/rob.cc
rename : cpu/o3/rob.hh => src/cpu/o3/rob.hh
rename : cpu/o3/rob_impl.hh => src/cpu/o3/rob_impl.hh
rename : cpu/o3/sat_counter.cc => src/cpu/o3/sat_counter.cc
rename : cpu/o3/sat_counter.hh => src/cpu/o3/sat_counter.hh
rename : cpu/o3/store_set.cc => src/cpu/o3/store_set.cc
rename : cpu/o3/store_set.hh => src/cpu/o3/store_set.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/op_class.cc => src/cpu/op_class.cc
rename : cpu/op_class.hh => src/cpu/op_class.hh
rename : cpu/ozone/cpu.cc => src/cpu/ozone/cpu.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/ozone/ea_list.cc => src/cpu/ozone/ea_list.cc
rename : cpu/ozone/ea_list.hh => src/cpu/ozone/ea_list.hh
rename : cpu/pc_event.cc => src/cpu/pc_event.cc
rename : cpu/pc_event.hh => src/cpu/pc_event.hh
rename : cpu/profile.cc => src/cpu/profile.cc
rename : cpu/profile.hh => src/cpu/profile.hh
rename : cpu/simple/atomic.cc => src/cpu/simple/atomic.cc
rename : cpu/simple/atomic.hh => src/cpu/simple/atomic.hh
rename : cpu/simple/base.cc => src/cpu/simple/base.cc
rename : cpu/simple/base.hh => src/cpu/simple/base.hh
rename : cpu/simple/timing.cc => src/cpu/simple/timing.cc
rename : cpu/simple/timing.hh => src/cpu/simple/timing.hh
rename : cpu/smt.hh => src/cpu/smt.hh
rename : cpu/static_inst.cc => src/cpu/static_inst.cc
rename : cpu/static_inst.hh => src/cpu/static_inst.hh
rename : cpu/trace/opt_cpu.cc => src/cpu/trace/opt_cpu.cc
rename : cpu/trace/opt_cpu.hh => src/cpu/trace/opt_cpu.hh
rename : cpu/trace/reader/ibm_reader.cc => src/cpu/trace/reader/ibm_reader.cc
rename : cpu/trace/reader/ibm_reader.hh => src/cpu/trace/reader/ibm_reader.hh
rename : cpu/trace/reader/itx_reader.cc => src/cpu/trace/reader/itx_reader.cc
rename : cpu/trace/reader/itx_reader.hh => src/cpu/trace/reader/itx_reader.hh
rename : cpu/trace/reader/m5_reader.cc => src/cpu/trace/reader/m5_reader.cc
rename : cpu/trace/reader/m5_reader.hh => src/cpu/trace/reader/m5_reader.hh
rename : cpu/trace/reader/mem_trace_reader.cc => src/cpu/trace/reader/mem_trace_reader.cc
rename : cpu/trace/reader/mem_trace_reader.hh => src/cpu/trace/reader/mem_trace_reader.hh
rename : cpu/trace/trace_cpu.cc => src/cpu/trace/trace_cpu.cc
rename : cpu/trace/trace_cpu.hh => src/cpu/trace/trace_cpu.hh
rename : dev/alpha_access.h => src/dev/alpha_access.h
rename : dev/alpha_console.cc => src/dev/alpha_console.cc
rename : dev/alpha_console.hh => src/dev/alpha_console.hh
rename : dev/baddev.cc => src/dev/baddev.cc
rename : dev/baddev.hh => src/dev/baddev.hh
rename : dev/disk_image.cc => src/dev/disk_image.cc
rename : dev/disk_image.hh => src/dev/disk_image.hh
rename : dev/etherbus.cc => src/dev/etherbus.cc
rename : dev/etherbus.hh => src/dev/etherbus.hh
rename : dev/etherdump.cc => src/dev/etherdump.cc
rename : dev/etherdump.hh => src/dev/etherdump.hh
rename : dev/etherint.cc => src/dev/etherint.cc
rename : dev/etherint.hh => src/dev/etherint.hh
rename : dev/etherlink.cc => src/dev/etherlink.cc
rename : dev/etherlink.hh => src/dev/etherlink.hh
rename : dev/etherpkt.cc => src/dev/etherpkt.cc
rename : dev/etherpkt.hh => src/dev/etherpkt.hh
rename : dev/ethertap.cc => src/dev/ethertap.cc
rename : dev/ethertap.hh => src/dev/ethertap.hh
rename : dev/ide_atareg.h => src/dev/ide_atareg.h
rename : dev/ide_ctrl.cc => src/dev/ide_ctrl.cc
rename : dev/ide_ctrl.hh => src/dev/ide_ctrl.hh
rename : dev/ide_disk.cc => src/dev/ide_disk.cc
rename : dev/ide_disk.hh => src/dev/ide_disk.hh
rename : dev/ide_wdcreg.h => src/dev/ide_wdcreg.h
rename : dev/io_device.cc => src/dev/io_device.cc
rename : dev/io_device.hh => src/dev/io_device.hh
rename : dev/isa_fake.cc => src/dev/isa_fake.cc
rename : dev/isa_fake.hh => src/dev/isa_fake.hh
rename : dev/ns_gige.cc => src/dev/ns_gige.cc
rename : dev/ns_gige.hh => src/dev/ns_gige.hh
rename : dev/ns_gige_reg.h => src/dev/ns_gige_reg.h
rename : dev/pciconfigall.cc => src/dev/pciconfigall.cc
rename : dev/pciconfigall.hh => src/dev/pciconfigall.hh
rename : dev/pcidev.cc => src/dev/pcidev.cc
rename : dev/pcidev.hh => src/dev/pcidev.hh
rename : dev/pcireg.h => src/dev/pcireg.h
rename : dev/pitreg.h => src/dev/pitreg.h
rename : dev/pktfifo.cc => src/dev/pktfifo.cc
rename : dev/pktfifo.hh => src/dev/pktfifo.hh
rename : dev/platform.cc => src/dev/platform.cc
rename : dev/platform.hh => src/dev/platform.hh
rename : dev/rtcreg.h => src/dev/rtcreg.h
rename : dev/simconsole.cc => src/dev/simconsole.cc
rename : dev/simconsole.hh => src/dev/simconsole.hh
rename : dev/simple_disk.cc => src/dev/simple_disk.cc
rename : dev/simple_disk.hh => src/dev/simple_disk.hh
rename : dev/sinic.cc => src/dev/sinic.cc
rename : dev/sinic.hh => src/dev/sinic.hh
rename : dev/sinicreg.hh => src/dev/sinicreg.hh
rename : dev/tsunami.cc => src/dev/tsunami.cc
rename : dev/tsunami.hh => src/dev/tsunami.hh
rename : dev/tsunami_cchip.cc => src/dev/tsunami_cchip.cc
rename : dev/tsunami_cchip.hh => src/dev/tsunami_cchip.hh
rename : dev/tsunami_io.cc => src/dev/tsunami_io.cc
rename : dev/tsunami_io.hh => src/dev/tsunami_io.hh
rename : dev/tsunami_pchip.cc => src/dev/tsunami_pchip.cc
rename : dev/tsunami_pchip.hh => src/dev/tsunami_pchip.hh
rename : dev/tsunamireg.h => src/dev/tsunamireg.h
rename : dev/uart.cc => src/dev/uart.cc
rename : dev/uart.hh => src/dev/uart.hh
rename : dev/uart8250.cc => src/dev/uart8250.cc
rename : dev/uart8250.hh => src/dev/uart8250.hh
rename : kern/kernel_stats.cc => src/kern/kernel_stats.cc
rename : kern/kernel_stats.hh => src/kern/kernel_stats.hh
rename : kern/linux/events.cc => src/kern/linux/events.cc
rename : kern/linux/events.hh => src/kern/linux/events.hh
rename : kern/linux/linux.hh => src/kern/linux/linux.hh
rename : kern/linux/linux_syscalls.cc => src/kern/linux/linux_syscalls.cc
rename : kern/linux/linux_syscalls.hh => src/kern/linux/linux_syscalls.hh
rename : kern/linux/printk.cc => src/kern/linux/printk.cc
rename : kern/linux/printk.hh => src/kern/linux/printk.hh
rename : kern/linux/sched.hh => src/kern/linux/sched.hh
rename : kern/solaris/solaris.hh => src/kern/solaris/solaris.hh
rename : kern/system_events.cc => src/kern/system_events.cc
rename : kern/system_events.hh => src/kern/system_events.hh
rename : kern/tru64/dump_mbuf.cc => src/kern/tru64/dump_mbuf.cc
rename : kern/tru64/dump_mbuf.hh => src/kern/tru64/dump_mbuf.hh
rename : kern/tru64/mbuf.hh => src/kern/tru64/mbuf.hh
rename : kern/tru64/printf.cc => src/kern/tru64/printf.cc
rename : kern/tru64/printf.hh => src/kern/tru64/printf.hh
rename : kern/tru64/tru64.hh => src/kern/tru64/tru64.hh
rename : kern/tru64/tru64_events.cc => src/kern/tru64/tru64_events.cc
rename : kern/tru64/tru64_events.hh => src/kern/tru64/tru64_events.hh
rename : kern/tru64/tru64_syscalls.cc => src/kern/tru64/tru64_syscalls.cc
rename : kern/tru64/tru64_syscalls.hh => src/kern/tru64/tru64_syscalls.hh
rename : mem/bridge.cc => src/mem/bridge.cc
rename : mem/bridge.hh => src/mem/bridge.hh
rename : mem/bus.cc => src/mem/bus.cc
rename : mem/bus.hh => src/mem/bus.hh
rename : mem/cache/prefetch/tagged_prefetcher_impl.hh => src/mem/cache/prefetch/tagged_prefetcher_impl.hh
rename : mem/config/prefetch.hh => src/mem/config/prefetch.hh
rename : mem/mem_object.cc => src/mem/mem_object.cc
rename : mem/mem_object.hh => src/mem/mem_object.hh
rename : mem/packet.cc => src/mem/packet.cc
rename : mem/packet.hh => src/mem/packet.hh
rename : mem/page_table.cc => src/mem/page_table.cc
rename : mem/page_table.hh => src/mem/page_table.hh
rename : mem/physical.cc => src/mem/physical.cc
rename : mem/physical.hh => src/mem/physical.hh
rename : mem/port.cc => src/mem/port.cc
rename : mem/port.hh => src/mem/port.hh
rename : mem/request.hh => src/mem/request.hh
rename : mem/translating_port.cc => src/mem/translating_port.cc
rename : mem/translating_port.hh => src/mem/translating_port.hh
rename : mem/vport.cc => src/mem/vport.cc
rename : mem/vport.hh => src/mem/vport.hh
rename : python/SConscript => src/python/SConscript
rename : python/m5/__init__.py => src/python/m5/__init__.py
rename : python/m5/config.py => src/python/m5/config.py
rename : python/m5/convert.py => src/python/m5/convert.py
rename : python/m5/multidict.py => src/python/m5/multidict.py
rename : python/m5/objects/AlphaConsole.py => src/python/m5/objects/AlphaConsole.py
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaFullCPU.py
rename : python/m5/objects/AlphaTLB.py => src/python/m5/objects/AlphaTLB.py
rename : python/m5/objects/BadDevice.py => src/python/m5/objects/BadDevice.py
rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py
rename : python/m5/objects/BaseCache.py => src/python/m5/objects/BaseCache.py
rename : python/m5/objects/Bridge.py => src/python/m5/objects/Bridge.py
rename : python/m5/objects/Bus.py => src/python/m5/objects/Bus.py
rename : python/m5/objects/CoherenceProtocol.py => src/python/m5/objects/CoherenceProtocol.py
rename : python/m5/objects/Device.py => src/python/m5/objects/Device.py
rename : python/m5/objects/DiskImage.py => src/python/m5/objects/DiskImage.py
rename : python/m5/objects/Ethernet.py => src/python/m5/objects/Ethernet.py
rename : python/m5/objects/Ide.py => src/python/m5/objects/Ide.py
rename : python/m5/objects/IntrControl.py => src/python/m5/objects/IntrControl.py
rename : python/m5/objects/MemObject.py => src/python/m5/objects/MemObject.py
rename : python/m5/objects/MemTest.py => src/python/m5/objects/MemTest.py
rename : python/m5/objects/Pci.py => src/python/m5/objects/Pci.py
rename : python/m5/objects/PhysicalMemory.py => src/python/m5/objects/PhysicalMemory.py
rename : python/m5/objects/Platform.py => src/python/m5/objects/Platform.py
rename : python/m5/objects/Process.py => src/python/m5/objects/Process.py
rename : python/m5/objects/Repl.py => src/python/m5/objects/Repl.py
rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py
rename : python/m5/objects/SimConsole.py => src/python/m5/objects/SimConsole.py
rename : python/m5/objects/SimpleDisk.py => src/python/m5/objects/SimpleDisk.py
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : python/m5/objects/Tsunami.py => src/python/m5/objects/Tsunami.py
rename : python/m5/objects/Uart.py => src/python/m5/objects/Uart.py
rename : python/m5/smartdict.py => src/python/m5/smartdict.py
rename : sim/async.hh => src/sim/async.hh
rename : sim/builder.cc => src/sim/builder.cc
rename : sim/builder.hh => src/sim/builder.hh
rename : sim/byteswap.hh => src/sim/byteswap.hh
rename : sim/debug.cc => src/sim/debug.cc
rename : sim/debug.hh => src/sim/debug.hh
rename : sim/eventq.cc => src/sim/eventq.cc
rename : sim/eventq.hh => src/sim/eventq.hh
rename : sim/faults.cc => src/sim/faults.cc
rename : sim/faults.hh => src/sim/faults.hh
rename : sim/host.hh => src/sim/host.hh
rename : sim/main.cc => src/sim/main.cc
rename : sim/param.cc => src/sim/param.cc
rename : sim/param.hh => src/sim/param.hh
rename : sim/process.cc => src/sim/process.cc
rename : sim/process.hh => src/sim/process.hh
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh
rename : sim/root.cc => src/sim/root.cc
rename : sim/serialize.cc => src/sim/serialize.cc
rename : sim/serialize.hh => src/sim/serialize.hh
rename : sim/sim_events.cc => src/sim/sim_events.cc
rename : sim/sim_events.hh => src/sim/sim_events.hh
rename : sim/sim_exit.hh => src/sim/sim_exit.hh
rename : sim/sim_object.cc => src/sim/sim_object.cc
rename : sim/sim_object.hh => src/sim/sim_object.hh
rename : sim/startup.cc => src/sim/startup.cc
rename : sim/startup.hh => src/sim/startup.hh
rename : sim/stat_control.cc => src/sim/stat_control.cc
rename : sim/stat_control.hh => src/sim/stat_control.hh
rename : sim/stats.hh => src/sim/stats.hh
rename : sim/syscall_emul.cc => src/sim/syscall_emul.cc
rename : sim/syscall_emul.hh => src/sim/syscall_emul.hh
rename : sim/system.cc => src/sim/system.cc
rename : sim/system.hh => src/sim/system.hh
rename : sim/vptr.hh => src/sim/vptr.hh
rename : test/Makefile => src/unittest/Makefile
rename : test/bitvectest.cc => src/unittest/bitvectest.cc
rename : test/circletest.cc => src/unittest/circletest.cc
rename : test/cprintftest.cc => src/unittest/cprintftest.cc
rename : test/foo.ini => src/unittest/foo.ini
rename : test/genini.py => src/unittest/genini.py
rename : test/initest.cc => src/unittest/initest.cc
rename : test/initest.ini => src/unittest/initest.ini
rename : test/lru_test.cc => src/unittest/lru_test.cc
rename : test/nmtest.cc => src/unittest/nmtest.cc
rename : test/offtest.cc => src/unittest/offtest.cc
rename : test/paramtest.cc => src/unittest/paramtest.cc
rename : test/rangetest.cc => src/unittest/rangetest.cc
rename : test/sized_test.cc => src/unittest/sized_test.cc
rename : test/stattest.cc => src/unittest/stattest.cc
rename : test/strnumtest.cc => src/unittest/strnumtest.cc
rename : test/symtest.cc => src/unittest/symtest.cc
rename : test/tokentest.cc => src/unittest/tokentest.cc
rename : test/tracetest.cc => src/unittest/tracetest.cc
extra : convert_revision : cab6a5271ca1b368193cd948e5d3dcc47ab1bd48
This commit is contained in:
Steve Reinhardt
@@ -1,74 +0,0 @@
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# Copyright (c) 2005 The Regents of The University of Michigan
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# All rights reserved.
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||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import sys, os
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# define this here so we can use it right away if necessary
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def panic(string):
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print >>sys.stderr, 'panic:', string
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sys.exit(1)
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def m5execfile(f, global_dict):
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# copy current sys.path
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oldpath = sys.path[:]
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# push file's directory onto front of path
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sys.path.insert(0, os.path.abspath(os.path.dirname(f)))
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execfile(f, global_dict)
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# restore original path
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sys.path = oldpath
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# Prepend given directory to system module search path.
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def AddToPath(path):
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# if it's a relative path and we know what directory the current
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# python script is in, make the path relative to that directory.
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if not os.path.isabs(path) and sys.path[0]:
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path = os.path.join(sys.path[0], path)
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path = os.path.realpath(path)
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# sys.path[0] should always refer to the current script's directory,
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# so place the new dir right after that.
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sys.path.insert(1, path)
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# find the m5 compile options: must be specified as a dict in
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# __main__.m5_build_env.
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import __main__
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if not hasattr(__main__, 'm5_build_env'):
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panic("__main__ must define m5_build_env")
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# make a SmartDict out of the build options for our local use
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import smartdict
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build_env = smartdict.SmartDict()
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build_env.update(__main__.m5_build_env)
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# make a SmartDict out of the OS environment too
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env = smartdict.SmartDict()
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env.update(os.environ)
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# import the main m5 config code
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from config import *
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# import the built-in object definitions
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from objects import *
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1323
python/m5/config.py
1323
python/m5/config.py
File diff suppressed because it is too large
Load Diff
@@ -1,227 +0,0 @@
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# Copyright (c) 2005 The Regents of The University of Michigan
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# All rights reserved.
|
||||
#
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# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# metric prefixes
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exa = 1.0e18
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peta = 1.0e15
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tera = 1.0e12
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giga = 1.0e9
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mega = 1.0e6
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kilo = 1.0e3
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milli = 1.0e-3
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micro = 1.0e-6
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nano = 1.0e-9
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pico = 1.0e-12
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femto = 1.0e-15
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atto = 1.0e-18
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# power of 2 prefixes
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kibi = 1024
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mebi = kibi * 1024
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gibi = mebi * 1024
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tebi = gibi * 1024
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pebi = tebi * 1024
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exbi = pebi * 1024
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# memory size configuration stuff
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def toFloat(value):
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if not isinstance(value, str):
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raise TypeError, "wrong type '%s' should be str" % type(value)
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if value.endswith('Ei'):
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return float(value[:-2]) * exbi
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elif value.endswith('Pi'):
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return float(value[:-2]) * pebi
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elif value.endswith('Ti'):
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return float(value[:-2]) * tebi
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elif value.endswith('Gi'):
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return float(value[:-2]) * gibi
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elif value.endswith('Mi'):
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return float(value[:-2]) * mebi
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elif value.endswith('ki'):
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return float(value[:-2]) * kibi
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elif value.endswith('E'):
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return float(value[:-1]) * exa
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elif value.endswith('P'):
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return float(value[:-1]) * peta
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elif value.endswith('T'):
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return float(value[:-1]) * tera
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elif value.endswith('G'):
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return float(value[:-1]) * giga
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elif value.endswith('M'):
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return float(value[:-1]) * mega
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elif value.endswith('k'):
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return float(value[:-1]) * kilo
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elif value.endswith('m'):
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||||
return float(value[:-1]) * milli
|
||||
elif value.endswith('u'):
|
||||
return float(value[:-1]) * micro
|
||||
elif value.endswith('n'):
|
||||
return float(value[:-1]) * nano
|
||||
elif value.endswith('p'):
|
||||
return float(value[:-1]) * pico
|
||||
elif value.endswith('f'):
|
||||
return float(value[:-1]) * femto
|
||||
else:
|
||||
return float(value)
|
||||
|
||||
def toInteger(value):
|
||||
value = toFloat(value)
|
||||
result = long(value)
|
||||
if value != result:
|
||||
raise ValueError, "cannot convert '%s' to integer" % value
|
||||
|
||||
return result
|
||||
|
||||
_bool_dict = {
|
||||
'true' : True, 't' : True, 'yes' : True, 'y' : True, '1' : True,
|
||||
'false' : False, 'f' : False, 'no' : False, 'n' : False, '0' : False
|
||||
}
|
||||
|
||||
def toBool(value):
|
||||
if not isinstance(value, str):
|
||||
raise TypeError, "wrong type '%s' should be str" % type(value)
|
||||
|
||||
value = value.lower()
|
||||
result = _bool_dict.get(value, None)
|
||||
if result == None:
|
||||
raise ValueError, "cannot convert '%s' to bool" % value
|
||||
return result
|
||||
|
||||
def toFrequency(value):
|
||||
if not isinstance(value, str):
|
||||
raise TypeError, "wrong type '%s' should be str" % type(value)
|
||||
|
||||
if value.endswith('THz'):
|
||||
return float(value[:-3]) * tera
|
||||
elif value.endswith('GHz'):
|
||||
return float(value[:-3]) * giga
|
||||
elif value.endswith('MHz'):
|
||||
return float(value[:-3]) * mega
|
||||
elif value.endswith('kHz'):
|
||||
return float(value[:-3]) * kilo
|
||||
elif value.endswith('Hz'):
|
||||
return float(value[:-2])
|
||||
|
||||
raise ValueError, "cannot convert '%s' to frequency" % value
|
||||
|
||||
def toLatency(value):
|
||||
if not isinstance(value, str):
|
||||
raise TypeError, "wrong type '%s' should be str" % type(value)
|
||||
|
||||
if value.endswith('ps'):
|
||||
return float(value[:-2]) * pico
|
||||
elif value.endswith('ns'):
|
||||
return float(value[:-2]) * nano
|
||||
elif value.endswith('us'):
|
||||
return float(value[:-2]) * micro
|
||||
elif value.endswith('ms'):
|
||||
return float(value[:-2]) * milli
|
||||
elif value.endswith('s'):
|
||||
return float(value[:-1])
|
||||
|
||||
raise ValueError, "cannot convert '%s' to latency" % value
|
||||
|
||||
def toClockPeriod(value):
|
||||
"""result is a clock period"""
|
||||
|
||||
if not isinstance(value, str):
|
||||
raise TypeError, "wrong type '%s' should be str" % type(value)
|
||||
|
||||
try:
|
||||
val = toFrequency(value)
|
||||
if val != 0:
|
||||
val = 1 / val
|
||||
return val
|
||||
except ValueError:
|
||||
pass
|
||||
|
||||
try:
|
||||
val = toLatency(value)
|
||||
return val
|
||||
except ValueError:
|
||||
pass
|
||||
|
||||
raise ValueError, "cannot convert '%s' to clock period" % value
|
||||
|
||||
|
||||
def toNetworkBandwidth(value):
|
||||
if not isinstance(value, str):
|
||||
raise TypeError, "wrong type '%s' should be str" % type(value)
|
||||
|
||||
if value.endswith('Tbps'):
|
||||
return float(value[:-4]) * tera
|
||||
elif value.endswith('Gbps'):
|
||||
return float(value[:-4]) * giga
|
||||
elif value.endswith('Mbps'):
|
||||
return float(value[:-4]) * mega
|
||||
elif value.endswith('kbps'):
|
||||
return float(value[:-4]) * kilo
|
||||
elif value.endswith('bps'):
|
||||
return float(value[:-3])
|
||||
else:
|
||||
return float(value)
|
||||
|
||||
raise ValueError, "cannot convert '%s' to network bandwidth" % value
|
||||
|
||||
def toMemoryBandwidth(value):
|
||||
if not isinstance(value, str):
|
||||
raise TypeError, "wrong type '%s' should be str" % type(value)
|
||||
|
||||
if value.endswith('PB/s'):
|
||||
return float(value[:-4]) * pebi
|
||||
elif value.endswith('TB/s'):
|
||||
return float(value[:-4]) * tebi
|
||||
elif value.endswith('GB/s'):
|
||||
return float(value[:-4]) * gibi
|
||||
elif value.endswith('MB/s'):
|
||||
return float(value[:-4]) * mebi
|
||||
elif value.endswith('kB/s'):
|
||||
return float(value[:-4]) * kibi
|
||||
elif value.endswith('B/s'):
|
||||
return float(value[:-3])
|
||||
|
||||
raise ValueError, "cannot convert '%s' to memory bandwidth" % value
|
||||
|
||||
def toMemorySize(value):
|
||||
if not isinstance(value, str):
|
||||
raise TypeError, "wrong type '%s' should be str" % type(value)
|
||||
|
||||
if value.endswith('PB'):
|
||||
return long(value[:-2]) * pebi
|
||||
elif value.endswith('TB'):
|
||||
return long(value[:-2]) * tebi
|
||||
elif value.endswith('GB'):
|
||||
return long(value[:-2]) * gibi
|
||||
elif value.endswith('MB'):
|
||||
return long(value[:-2]) * mebi
|
||||
elif value.endswith('kB'):
|
||||
return long(value[:-2]) * kibi
|
||||
elif value.endswith('B'):
|
||||
return long(value[:-1])
|
||||
|
||||
raise ValueError, "cannot convert '%s' to memory size" % value
|
||||
@@ -1,184 +0,0 @@
|
||||
# Copyright (c) 2005 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
__all__ = [ 'multidict' ]
|
||||
|
||||
class multidict(object):
|
||||
__nodefault = object()
|
||||
def __init__(self, parent = {}, **kwargs):
|
||||
self.dict = dict(**kwargs)
|
||||
self.parent = parent
|
||||
self.deleted = {}
|
||||
|
||||
def __str__(self):
|
||||
return str(dict(self.items()))
|
||||
|
||||
def __repr__(self):
|
||||
return `dict(self.items())`
|
||||
|
||||
def __contains__(self, key):
|
||||
return self.dict.has_key(key) or self.parent.has_key(key)
|
||||
|
||||
def __delitem__(self, key):
|
||||
try:
|
||||
del self.dict[key]
|
||||
except KeyError, e:
|
||||
if key in self.parent:
|
||||
self.deleted[key] = True
|
||||
else:
|
||||
raise KeyError, e
|
||||
|
||||
def __setitem__(self, key, value):
|
||||
self.deleted.pop(key, False)
|
||||
self.dict[key] = value
|
||||
|
||||
def __getitem__(self, key):
|
||||
try:
|
||||
return self.dict[key]
|
||||
except KeyError, e:
|
||||
if not self.deleted.get(key, False) and key in self.parent:
|
||||
return self.parent[key]
|
||||
else:
|
||||
raise KeyError, e
|
||||
|
||||
def __len__(self):
|
||||
return len(self.dict) + len(self.parent)
|
||||
|
||||
def next(self):
|
||||
for key,value in self.dict.items():
|
||||
yield key,value
|
||||
|
||||
if self.parent:
|
||||
for key,value in self.parent.next():
|
||||
if key not in self.dict and key not in self.deleted:
|
||||
yield key,value
|
||||
|
||||
def has_key(self, key):
|
||||
return key in self
|
||||
|
||||
def iteritems(self):
|
||||
for item in self.next():
|
||||
yield item
|
||||
|
||||
def items(self):
|
||||
return [ item for item in self.next() ]
|
||||
|
||||
def iterkeys(self):
|
||||
for key,value in self.next():
|
||||
yield key
|
||||
|
||||
def keys(self):
|
||||
return [ key for key,value in self.next() ]
|
||||
|
||||
def itervalues(self):
|
||||
for key,value in self.next():
|
||||
yield value
|
||||
|
||||
def values(self):
|
||||
return [ value for key,value in self.next() ]
|
||||
|
||||
def get(self, key, default=__nodefault):
|
||||
try:
|
||||
return self[key]
|
||||
except KeyError, e:
|
||||
if default != self.__nodefault:
|
||||
return default
|
||||
else:
|
||||
raise KeyError, e
|
||||
|
||||
def setdefault(self, key, default):
|
||||
try:
|
||||
return self[key]
|
||||
except KeyError:
|
||||
self.deleted.pop(key, False)
|
||||
self.dict[key] = default
|
||||
return default
|
||||
|
||||
def _dump(self):
|
||||
print 'multidict dump'
|
||||
node = self
|
||||
while isinstance(node, multidict):
|
||||
print ' ', node.dict
|
||||
node = node.parent
|
||||
|
||||
def _dumpkey(self, key):
|
||||
values = []
|
||||
node = self
|
||||
while isinstance(node, multidict):
|
||||
if key in node.dict:
|
||||
values.append(node.dict[key])
|
||||
node = node.parent
|
||||
print key, values
|
||||
|
||||
if __name__ == '__main__':
|
||||
test1 = multidict()
|
||||
test2 = multidict(test1)
|
||||
test3 = multidict(test2)
|
||||
test4 = multidict(test3)
|
||||
|
||||
test1['a'] = 'test1_a'
|
||||
test1['b'] = 'test1_b'
|
||||
test1['c'] = 'test1_c'
|
||||
test1['d'] = 'test1_d'
|
||||
test1['e'] = 'test1_e'
|
||||
|
||||
test2['a'] = 'test2_a'
|
||||
del test2['b']
|
||||
test2['c'] = 'test2_c'
|
||||
del test1['a']
|
||||
|
||||
test2.setdefault('f', multidict)
|
||||
|
||||
print 'test1>', test1.items()
|
||||
print 'test2>', test2.items()
|
||||
#print test1['a']
|
||||
print test1['b']
|
||||
print test1['c']
|
||||
print test1['d']
|
||||
print test1['e']
|
||||
|
||||
print test2['a']
|
||||
#print test2['b']
|
||||
print test2['c']
|
||||
print test2['d']
|
||||
print test2['e']
|
||||
|
||||
for key in test2.iterkeys():
|
||||
print key
|
||||
|
||||
test2.get('g', 'foo')
|
||||
#test2.get('b')
|
||||
test2.get('b', 'bar')
|
||||
test2.setdefault('b', 'blah')
|
||||
print test1
|
||||
print test2
|
||||
print `test2`
|
||||
|
||||
print len(test2)
|
||||
|
||||
test3['a'] = [ 0, 1, 2, 3 ]
|
||||
|
||||
print test4
|
||||
@@ -1,9 +0,0 @@
|
||||
from m5 import *
|
||||
from Device import BasicPioDevice
|
||||
|
||||
class AlphaConsole(BasicPioDevice):
|
||||
type = 'AlphaConsole'
|
||||
cpu = Param.BaseCPU(Parent.any, "Processor")
|
||||
disk = Param.SimpleDisk("Simple Disk")
|
||||
sim_console = Param.SimConsole(Parent.any, "The Simulator Console")
|
||||
system = Param.AlphaSystem(Parent.any, "system object")
|
||||
@@ -1,80 +0,0 @@
|
||||
from m5 import *
|
||||
from BaseCPU import BaseCPU
|
||||
|
||||
class DerivAlphaFullCPU(BaseCPU):
|
||||
type = 'DerivAlphaFullCPU'
|
||||
|
||||
numThreads = Param.Unsigned("number of HW thread contexts")
|
||||
|
||||
if not build_env['FULL_SYSTEM']:
|
||||
mem = Param.FunctionalMemory(NULL, "memory")
|
||||
|
||||
decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
|
||||
renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
|
||||
iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
|
||||
"delay")
|
||||
commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
|
||||
fetchWidth = Param.Unsigned("Fetch width")
|
||||
|
||||
renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
|
||||
iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
|
||||
"delay")
|
||||
commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
|
||||
fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
|
||||
decodeWidth = Param.Unsigned("Decode width")
|
||||
|
||||
iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
|
||||
"delay")
|
||||
commitToRenameDelay = Param.Unsigned("Commit to rename delay")
|
||||
decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
|
||||
renameWidth = Param.Unsigned("Rename width")
|
||||
|
||||
commitToIEWDelay = Param.Unsigned("Commit to "
|
||||
"Issue/Execute/Writeback delay")
|
||||
renameToIEWDelay = Param.Unsigned("Rename to "
|
||||
"Issue/Execute/Writeback delay")
|
||||
issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
|
||||
"to the IEW stage)")
|
||||
issueWidth = Param.Unsigned("Issue width")
|
||||
executeWidth = Param.Unsigned("Execute width")
|
||||
executeIntWidth = Param.Unsigned("Integer execute width")
|
||||
executeFloatWidth = Param.Unsigned("Floating point execute width")
|
||||
executeBranchWidth = Param.Unsigned("Branch execute width")
|
||||
executeMemoryWidth = Param.Unsigned("Memory execute width")
|
||||
|
||||
iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
|
||||
"delay")
|
||||
renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
|
||||
commitWidth = Param.Unsigned("Commit width")
|
||||
squashWidth = Param.Unsigned("Squash width")
|
||||
|
||||
local_predictor_size = Param.Unsigned("Size of local predictor")
|
||||
local_ctr_bits = Param.Unsigned("Bits per counter")
|
||||
local_history_table_size = Param.Unsigned("Size of local history table")
|
||||
local_history_bits = Param.Unsigned("Bits for the local history")
|
||||
global_predictor_size = Param.Unsigned("Size of global predictor")
|
||||
global_ctr_bits = Param.Unsigned("Bits per counter")
|
||||
global_history_bits = Param.Unsigned("Bits of history")
|
||||
choice_predictor_size = Param.Unsigned("Size of choice predictor")
|
||||
choice_ctr_bits = Param.Unsigned("Bits of choice counters")
|
||||
|
||||
BTBEntries = Param.Unsigned("Number of BTB entries")
|
||||
BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
|
||||
|
||||
RASSize = Param.Unsigned("RAS size")
|
||||
|
||||
LQEntries = Param.Unsigned("Number of load queue entries")
|
||||
SQEntries = Param.Unsigned("Number of store queue entries")
|
||||
LFSTSize = Param.Unsigned("Last fetched store table size")
|
||||
SSITSize = Param.Unsigned("Store set ID table size")
|
||||
|
||||
numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
|
||||
numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
|
||||
"registers")
|
||||
numIQEntries = Param.Unsigned("Number of instruction queue entries")
|
||||
numROBEntries = Param.Unsigned("Number of reorder buffer entries")
|
||||
|
||||
instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
|
||||
|
||||
function_trace = Param.Bool(False, "Enable function trace")
|
||||
function_trace_start = Param.Tick(0, "Cycle to start function trace")
|
||||
@@ -1,13 +0,0 @@
|
||||
from m5 import *
|
||||
class AlphaTLB(SimObject):
|
||||
type = 'AlphaTLB'
|
||||
abstract = True
|
||||
size = Param.Int("TLB size")
|
||||
|
||||
class AlphaDTB(AlphaTLB):
|
||||
type = 'AlphaDTB'
|
||||
size = 64
|
||||
|
||||
class AlphaITB(AlphaTLB):
|
||||
type = 'AlphaITB'
|
||||
size = 48
|
||||
@@ -1,6 +0,0 @@
|
||||
from m5 import *
|
||||
from Device import BasicPioDevice
|
||||
|
||||
class BadDevice(BasicPioDevice):
|
||||
type = 'BadDevice'
|
||||
devicename = Param.String("Name of device to error on")
|
||||
@@ -1,27 +0,0 @@
|
||||
from m5 import *
|
||||
class BaseCPU(SimObject):
|
||||
type = 'BaseCPU'
|
||||
abstract = True
|
||||
mem = Param.MemObject("memory")
|
||||
|
||||
if build_env['FULL_SYSTEM']:
|
||||
dtb = Param.AlphaDTB("Data TLB")
|
||||
itb = Param.AlphaITB("Instruction TLB")
|
||||
system = Param.System(Parent.any, "system object")
|
||||
cpu_id = Param.Int(-1, "CPU identifier")
|
||||
else:
|
||||
workload = VectorParam.Process("processes to run")
|
||||
|
||||
max_insts_all_threads = Param.Counter(0,
|
||||
"terminate when all threads have reached this inst count")
|
||||
max_insts_any_thread = Param.Counter(0,
|
||||
"terminate when any thread reaches this inst count")
|
||||
max_loads_all_threads = Param.Counter(0,
|
||||
"terminate when all threads have reached this load count")
|
||||
max_loads_any_thread = Param.Counter(0,
|
||||
"terminate when any thread reaches this load count")
|
||||
|
||||
defer_registration = Param.Bool(False,
|
||||
"defer registration with system (for sampling)")
|
||||
|
||||
clock = Param.Clock(Parent.clock, "clock speed")
|
||||
@@ -1,65 +0,0 @@
|
||||
from m5 import *
|
||||
from BaseMem import BaseMem
|
||||
|
||||
class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
|
||||
|
||||
class BaseCache(BaseMem):
|
||||
type = 'BaseCache'
|
||||
adaptive_compression = Param.Bool(False,
|
||||
"Use an adaptive compression scheme")
|
||||
assoc = Param.Int("associativity")
|
||||
block_size = Param.Int("block size in bytes")
|
||||
compressed_bus = Param.Bool(False,
|
||||
"This cache connects to a compressed memory")
|
||||
compression_latency = Param.Latency('0ns',
|
||||
"Latency in cycles of compression algorithm")
|
||||
do_copy = Param.Bool(False, "perform fast copies in the cache")
|
||||
hash_delay = Param.Int(1, "time in cycles of hash access")
|
||||
in_bus = Param.Bus(NULL, "incoming bus object")
|
||||
lifo = Param.Bool(False,
|
||||
"whether this NIC partition should use LIFO repl. policy")
|
||||
max_miss_count = Param.Counter(0,
|
||||
"number of misses to handle before calling exit")
|
||||
mem_trace = Param.MemTraceWriter(NULL,
|
||||
"memory trace writer to record accesses")
|
||||
mshrs = Param.Int("number of MSHRs (max outstanding requests)")
|
||||
out_bus = Param.Bus("outgoing bus object")
|
||||
prioritizeRequests = Param.Bool(False,
|
||||
"always service demand misses first")
|
||||
protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use")
|
||||
repl = Param.Repl(NULL, "replacement policy")
|
||||
size = Param.MemorySize("capacity in bytes")
|
||||
split = Param.Bool(False, "whether or not this cache is split")
|
||||
split_size = Param.Int(0,
|
||||
"How many ways of the cache belong to CPU/LRU partition")
|
||||
store_compressed = Param.Bool(False,
|
||||
"Store compressed data in the cache")
|
||||
subblock_size = Param.Int(0,
|
||||
"Size of subblock in IIC used for compression")
|
||||
tgts_per_mshr = Param.Int("max number of accesses per MSHR")
|
||||
trace_addr = Param.Addr(0, "address to trace")
|
||||
two_queue = Param.Bool(False,
|
||||
"whether the lifo should have two queue replacement")
|
||||
write_buffers = Param.Int(8, "number of write buffers")
|
||||
prefetch_miss = Param.Bool(False,
|
||||
"wheter you are using the hardware prefetcher from Miss stream")
|
||||
prefetch_access = Param.Bool(False,
|
||||
"wheter you are using the hardware prefetcher from Access stream")
|
||||
prefetcher_size = Param.Int(100,
|
||||
"Number of entries in the harware prefetch queue")
|
||||
prefetch_past_page = Param.Bool(False,
|
||||
"Allow prefetches to cross virtual page boundaries")
|
||||
prefetch_serial_squash = Param.Bool(False,
|
||||
"Squash prefetches with a later time on a subsequent miss")
|
||||
prefetch_degree = Param.Int(1,
|
||||
"Degree of the prefetch depth")
|
||||
prefetch_latency = Param.Tick(10,
|
||||
"Latency of the prefetcher")
|
||||
prefetch_policy = Param.Prefetch('none',
|
||||
"Type of prefetcher to use")
|
||||
prefetch_cache_check_push = Param.Bool(True,
|
||||
"Check if in cash on push or pop of prefetch queue")
|
||||
prefetch_use_cpu_id = Param.Bool(True,
|
||||
"Use the CPU ID to seperate calculations of prefetches")
|
||||
prefetch_data_accesses_only = Param.Bool(False,
|
||||
"Only prefetch on data not on instruction accesses")
|
||||
@@ -1,9 +0,0 @@
|
||||
from m5 import *
|
||||
from MemObject import MemObject
|
||||
|
||||
class Bridge(MemObject):
|
||||
type = 'Bridge'
|
||||
queue_size_a = Param.Int(16, "The number of requests to buffer")
|
||||
queue_size_b = Param.Int(16, "The number of requests to buffer")
|
||||
delay = Param.Latency('0ns', "The latency of this bridge")
|
||||
write_ack = Param.Bool(False, "Should this bridge ack writes")
|
||||
@@ -1,6 +0,0 @@
|
||||
from m5 import *
|
||||
from MemObject import MemObject
|
||||
|
||||
class Bus(MemObject):
|
||||
type = 'Bus'
|
||||
bus_id = Param.Int(0, "blah")
|
||||
@@ -1,7 +0,0 @@
|
||||
from m5 import *
|
||||
class Coherence(Enum): vals = ['uni', 'msi', 'mesi', 'mosi', 'moesi']
|
||||
|
||||
class CoherenceProtocol(SimObject):
|
||||
type = 'CoherenceProtocol'
|
||||
do_upgrades = Param.Bool(True, "use upgrade transactions?")
|
||||
protocol = Param.Coherence("name of coherence protocol")
|
||||
@@ -1,18 +0,0 @@
|
||||
from m5 import *
|
||||
from MemObject import MemObject
|
||||
|
||||
class PioDevice(MemObject):
|
||||
type = 'PioDevice'
|
||||
abstract = True
|
||||
platform = Param.Platform(Parent.any, "Platform this device is part of")
|
||||
system = Param.System(Parent.any, "System this device is part of")
|
||||
|
||||
class BasicPioDevice(PioDevice):
|
||||
type = 'BasicPioDevice'
|
||||
abstract = True
|
||||
pio_addr = Param.Addr("Device Address")
|
||||
pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
|
||||
|
||||
class DmaDevice(PioDevice):
|
||||
type = 'DmaDevice'
|
||||
abstract = True
|
||||
@@ -1,15 +0,0 @@
|
||||
from m5 import *
|
||||
class DiskImage(SimObject):
|
||||
type = 'DiskImage'
|
||||
abstract = True
|
||||
image_file = Param.String("disk image file")
|
||||
read_only = Param.Bool(False, "read only image")
|
||||
|
||||
class RawDiskImage(DiskImage):
|
||||
type = 'RawDiskImage'
|
||||
|
||||
class CowDiskImage(DiskImage):
|
||||
type = 'CowDiskImage'
|
||||
child = Param.DiskImage("child image")
|
||||
table_size = Param.Int(65536, "initial table size")
|
||||
image_file = ''
|
||||
@@ -1,115 +0,0 @@
|
||||
from m5 import *
|
||||
from Device import DmaDevice
|
||||
from Pci import PciDevice
|
||||
|
||||
class EtherInt(SimObject):
|
||||
type = 'EtherInt'
|
||||
abstract = True
|
||||
peer = Param.EtherInt(NULL, "peer interface")
|
||||
|
||||
class EtherLink(SimObject):
|
||||
type = 'EtherLink'
|
||||
int1 = Param.EtherInt("interface 1")
|
||||
int2 = Param.EtherInt("interface 2")
|
||||
delay = Param.Latency('0us', "packet transmit delay")
|
||||
delay_var = Param.Latency('0ns', "packet transmit delay variability")
|
||||
speed = Param.NetworkBandwidth('1Gbps', "link speed")
|
||||
dump = Param.EtherDump(NULL, "dump object")
|
||||
|
||||
class EtherBus(SimObject):
|
||||
type = 'EtherBus'
|
||||
loopback = Param.Bool(True, "send packet back to the sending interface")
|
||||
dump = Param.EtherDump(NULL, "dump object")
|
||||
speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
|
||||
|
||||
class EtherTap(EtherInt):
|
||||
type = 'EtherTap'
|
||||
bufsz = Param.Int(10000, "tap buffer size")
|
||||
dump = Param.EtherDump(NULL, "dump object")
|
||||
port = Param.UInt16(3500, "tap port")
|
||||
|
||||
class EtherDump(SimObject):
|
||||
type = 'EtherDump'
|
||||
file = Param.String("dump file")
|
||||
maxlen = Param.Int(96, "max portion of packet data to dump")
|
||||
|
||||
if build_env['ALPHA_TLASER']:
|
||||
|
||||
class EtherDev(DmaDevice):
|
||||
type = 'EtherDev'
|
||||
hardware_address = Param.EthernetAddr(NextEthernetAddr,
|
||||
"Ethernet Hardware Address")
|
||||
|
||||
dma_data_free = Param.Bool(False, "DMA of Data is free")
|
||||
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
|
||||
dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
|
||||
dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
|
||||
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
|
||||
dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
|
||||
dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
|
||||
|
||||
rx_filter = Param.Bool(True, "Enable Receive Filter")
|
||||
rx_delay = Param.Latency('1us', "Receive Delay")
|
||||
tx_delay = Param.Latency('1us', "Transmit Delay")
|
||||
|
||||
intr_delay = Param.Latency('0us', "Interrupt Delay")
|
||||
payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
|
||||
physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
|
||||
tlaser = Param.Turbolaser(Parent.any, "Turbolaser")
|
||||
|
||||
class EtherDevInt(EtherInt):
|
||||
type = 'EtherDevInt'
|
||||
device = Param.EtherDev("Ethernet device of this interface")
|
||||
|
||||
class EtherDevBase(PciDevice):
|
||||
hardware_address = Param.EthernetAddr(NextEthernetAddr,
|
||||
"Ethernet Hardware Address")
|
||||
|
||||
clock = Param.Clock('0ns', "State machine processor frequency")
|
||||
|
||||
dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
|
||||
dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
|
||||
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
|
||||
dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
|
||||
|
||||
rx_delay = Param.Latency('1us', "Receive Delay")
|
||||
tx_delay = Param.Latency('1us', "Transmit Delay")
|
||||
rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo")
|
||||
tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo")
|
||||
|
||||
rx_filter = Param.Bool(True, "Enable Receive Filter")
|
||||
intr_delay = Param.Latency('10us', "Interrupt propagation delay")
|
||||
rx_thread = Param.Bool(False, "dedicated kernel thread for transmit")
|
||||
tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
|
||||
rss = Param.Bool(False, "Receive Side Scaling")
|
||||
|
||||
class NSGigE(EtherDevBase):
|
||||
type = 'NSGigE'
|
||||
|
||||
dma_data_free = Param.Bool(False, "DMA of Data is free")
|
||||
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
|
||||
dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
|
||||
|
||||
|
||||
class NSGigEInt(EtherInt):
|
||||
type = 'NSGigEInt'
|
||||
device = Param.NSGigE("Ethernet device of this interface")
|
||||
|
||||
class Sinic(EtherDevBase):
|
||||
type = 'Sinic'
|
||||
|
||||
rx_max_copy = Param.MemorySize('1514B', "rx max copy")
|
||||
tx_max_copy = Param.MemorySize('16kB', "tx max copy")
|
||||
rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
|
||||
rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold")
|
||||
rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold")
|
||||
tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold")
|
||||
tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold")
|
||||
virtual_count = Param.UInt32(1, "Virtualized SINIC")
|
||||
zero_copy = Param.Bool(False, "Zero copy receive")
|
||||
delay_copy = Param.Bool(False, "Delayed copy transmit")
|
||||
virtual_addr = Param.Bool(False, "Virtual addressing")
|
||||
|
||||
class SinicInt(EtherInt):
|
||||
type = 'SinicInt'
|
||||
device = Param.Sinic("Ethernet device of this interface")
|
||||
@@ -1,14 +0,0 @@
|
||||
from m5 import *
|
||||
from Pci import PciDevice
|
||||
|
||||
class IdeID(Enum): vals = ['master', 'slave']
|
||||
|
||||
class IdeDisk(SimObject):
|
||||
type = 'IdeDisk'
|
||||
delay = Param.Latency('1us', "Fixed disk delay in microseconds")
|
||||
driveID = Param.IdeID('master', "Drive ID")
|
||||
image = Param.DiskImage("Disk image")
|
||||
|
||||
class IdeController(PciDevice):
|
||||
type = 'IdeController'
|
||||
disks = VectorParam.IdeDisk("IDE disks attached to this controller")
|
||||
@@ -1,4 +0,0 @@
|
||||
from m5 import *
|
||||
class IntrControl(SimObject):
|
||||
type = 'IntrControl'
|
||||
cpu = Param.BaseCPU(Parent.any, "the cpu")
|
||||
@@ -1,5 +0,0 @@
|
||||
from m5 import *
|
||||
|
||||
class MemObject(SimObject):
|
||||
type = 'MemObject'
|
||||
abstract = True
|
||||
@@ -1,19 +0,0 @@
|
||||
from m5 import *
|
||||
class MemTest(SimObject):
|
||||
type = 'MemTest'
|
||||
cache = Param.BaseCache("L1 cache")
|
||||
check_mem = Param.FunctionalMemory("check memory")
|
||||
main_mem = Param.FunctionalMemory("hierarchical memory")
|
||||
max_loads = Param.Counter("number of loads to execute")
|
||||
memory_size = Param.Int(65536, "memory size")
|
||||
percent_copies = Param.Percent(0, "target copy percentage")
|
||||
percent_dest_unaligned = Param.Percent(50,
|
||||
"percent of copy dest address that are unaligned")
|
||||
percent_reads = Param.Percent(65, "target read percentage")
|
||||
percent_source_unaligned = Param.Percent(50,
|
||||
"percent of copy source address that are unaligned")
|
||||
percent_uncacheable = Param.Percent(10,
|
||||
"target uncacheable percentage")
|
||||
progress_interval = Param.Counter(1000000,
|
||||
"progress report interval (in accesses)")
|
||||
trace_addr = Param.Addr(0, "address to trace")
|
||||
@@ -1,55 +0,0 @@
|
||||
from m5 import *
|
||||
from Device import BasicPioDevice, DmaDevice
|
||||
|
||||
class PciConfigData(SimObject):
|
||||
type = 'PciConfigData'
|
||||
VendorID = Param.UInt16("Vendor ID")
|
||||
DeviceID = Param.UInt16("Device ID")
|
||||
Command = Param.UInt16(0, "Command")
|
||||
Status = Param.UInt16(0, "Status")
|
||||
Revision = Param.UInt8(0, "Device")
|
||||
ProgIF = Param.UInt8(0, "Programming Interface")
|
||||
SubClassCode = Param.UInt8(0, "Sub-Class Code")
|
||||
ClassCode = Param.UInt8(0, "Class Code")
|
||||
CacheLineSize = Param.UInt8(0, "System Cacheline Size")
|
||||
LatencyTimer = Param.UInt8(0, "PCI Latency Timer")
|
||||
HeaderType = Param.UInt8(0, "PCI Header Type")
|
||||
BIST = Param.UInt8(0, "Built In Self Test")
|
||||
|
||||
BAR0 = Param.UInt32(0x00, "Base Address Register 0")
|
||||
BAR1 = Param.UInt32(0x00, "Base Address Register 1")
|
||||
BAR2 = Param.UInt32(0x00, "Base Address Register 2")
|
||||
BAR3 = Param.UInt32(0x00, "Base Address Register 3")
|
||||
BAR4 = Param.UInt32(0x00, "Base Address Register 4")
|
||||
BAR5 = Param.UInt32(0x00, "Base Address Register 5")
|
||||
BAR0Size = Param.MemorySize32('0B', "Base Address Register 0 Size")
|
||||
BAR1Size = Param.MemorySize32('0B', "Base Address Register 1 Size")
|
||||
BAR2Size = Param.MemorySize32('0B', "Base Address Register 2 Size")
|
||||
BAR3Size = Param.MemorySize32('0B', "Base Address Register 3 Size")
|
||||
BAR4Size = Param.MemorySize32('0B', "Base Address Register 4 Size")
|
||||
BAR5Size = Param.MemorySize32('0B', "Base Address Register 5 Size")
|
||||
|
||||
CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
|
||||
SubsystemID = Param.UInt16(0x00, "Subsystem ID")
|
||||
SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID")
|
||||
ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address")
|
||||
InterruptLine = Param.UInt8(0x00, "Interrupt Line")
|
||||
InterruptPin = Param.UInt8(0x00, "Interrupt Pin")
|
||||
MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
|
||||
MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
|
||||
|
||||
class PciConfigAll(BasicPioDevice):
|
||||
type = 'PciConfigAll'
|
||||
|
||||
class PciDevice(DmaDevice):
|
||||
type = 'PciDevice'
|
||||
abstract = True
|
||||
pci_bus = Param.Int("PCI bus")
|
||||
pci_dev = Param.Int("PCI device number")
|
||||
pci_func = Param.Int("PCI function code")
|
||||
pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
|
||||
configdata = Param.PciConfigData(Parent.any, "PCI Config data")
|
||||
configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
|
||||
|
||||
class PciFake(PciDevice):
|
||||
type = 'PciFake'
|
||||
@@ -1,8 +0,0 @@
|
||||
from m5 import *
|
||||
from MemObject import *
|
||||
|
||||
class PhysicalMemory(MemObject):
|
||||
type = 'PhysicalMemory'
|
||||
range = Param.AddrRange("Device Address")
|
||||
file = Param.String('', "memory mapped file")
|
||||
latency = Param.Latency(Parent.clock, "latency of an access")
|
||||
@@ -1,5 +0,0 @@
|
||||
from m5 import *
|
||||
class Platform(SimObject):
|
||||
type = 'Platform'
|
||||
abstract = True
|
||||
intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
|
||||
@@ -1,27 +0,0 @@
|
||||
from m5 import *
|
||||
class Process(SimObject):
|
||||
type = 'Process'
|
||||
abstract = True
|
||||
output = Param.String('cout', 'filename for stdout/stderr')
|
||||
system = Param.System(Parent.any, "system process will run on")
|
||||
|
||||
class LiveProcess(Process):
|
||||
type = 'LiveProcess'
|
||||
executable = Param.String('', "executable (overrides cmd[0] if set)")
|
||||
cmd = VectorParam.String("command line (executable plus arguments)")
|
||||
env = VectorParam.String('', "environment settings")
|
||||
input = Param.String('cin', "filename for stdin")
|
||||
|
||||
class AlphaLiveProcess(LiveProcess):
|
||||
type = 'AlphaLiveProcess'
|
||||
|
||||
class SparcLiveProcess(LiveProcess):
|
||||
type = 'SparcLiveProcess'
|
||||
|
||||
class MipsLiveProcess(LiveProcess):
|
||||
type = 'MipsLiveProcess'
|
||||
|
||||
class EioProcess(Process):
|
||||
type = 'EioProcess'
|
||||
chkpt = Param.String('', "EIO checkpoint file name (optional)")
|
||||
file = Param.String("EIO trace file name")
|
||||
@@ -1,10 +0,0 @@
|
||||
from m5 import *
|
||||
class Repl(SimObject):
|
||||
type = 'Repl'
|
||||
abstract = True
|
||||
|
||||
class GenRepl(Repl):
|
||||
type = 'GenRepl'
|
||||
fresh_res = Param.Int("associativity")
|
||||
num_pools = Param.Int("capacity in bytes")
|
||||
pool_res = Param.Int("block size in bytes")
|
||||
@@ -1,23 +0,0 @@
|
||||
from m5 import *
|
||||
from Serialize import Serialize
|
||||
from Statistics import Statistics
|
||||
from Trace import Trace
|
||||
from ExeTrace import ExecutionTrace
|
||||
from Debug import Debug
|
||||
|
||||
class Root(SimObject):
|
||||
type = 'Root'
|
||||
clock = Param.RootClock('200MHz', "tick frequency")
|
||||
max_tick = Param.Tick('0', "maximum simulation ticks (0 = infinite)")
|
||||
progress_interval = Param.Tick('0',
|
||||
"print a progress message every n ticks (0 = never)")
|
||||
output_file = Param.String('cout', "file to dump simulator output to")
|
||||
checkpoint = Param.String('', "checkpoint file to load")
|
||||
# stats = Param.Statistics(Statistics(), "statistics object")
|
||||
# trace = Param.Trace(Trace(), "trace object")
|
||||
# serialize = Param.Serialize(Serialize(), "checkpoint generation options")
|
||||
stats = Statistics()
|
||||
trace = Trace()
|
||||
exetrace = ExecutionTrace()
|
||||
serialize = Serialize()
|
||||
debug = Debug()
|
||||
@@ -1,12 +0,0 @@
|
||||
from m5 import *
|
||||
class ConsoleListener(SimObject):
|
||||
type = 'ConsoleListener'
|
||||
port = Param.TcpPort(3456, "listen port")
|
||||
|
||||
class SimConsole(SimObject):
|
||||
type = 'SimConsole'
|
||||
append_name = Param.Bool(True, "append name() to filename")
|
||||
intr_control = Param.IntrControl(Parent.any, "interrupt controller")
|
||||
listener = Param.ConsoleListener("console listener")
|
||||
number = Param.Int(0, "console number")
|
||||
output = Param.String('console', "file to dump output to")
|
||||
@@ -1,5 +0,0 @@
|
||||
from m5 import *
|
||||
class SimpleDisk(SimObject):
|
||||
type = 'SimpleDisk'
|
||||
disk = Param.DiskImage("Disk Image")
|
||||
system = Param.System(Parent.any, "Sysetm Pointer")
|
||||
@@ -1,21 +0,0 @@
|
||||
from m5 import *
|
||||
|
||||
class System(SimObject):
|
||||
type = 'System'
|
||||
physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
|
||||
if build_env['FULL_SYSTEM']:
|
||||
boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
|
||||
"boot processor frequency")
|
||||
init_param = Param.UInt64(0, "numerical value to pass into simulator")
|
||||
bin = Param.Bool(False, "is this system binned")
|
||||
binned_fns = VectorParam.String([], "functions broken down and binned")
|
||||
boot_osflags = Param.String("a", "boot flags to pass to the kernel")
|
||||
kernel = Param.String("file that contains the kernel code")
|
||||
readfile = Param.String("", "file to read startup script from")
|
||||
|
||||
class AlphaSystem(System):
|
||||
type = 'AlphaSystem'
|
||||
console = Param.String("file that contains the console code")
|
||||
pal = Param.String("file that contains palcode")
|
||||
system_type = Param.UInt64("Type of system we are emulating")
|
||||
system_rev = Param.UInt64("Revision of system we are emulating")
|
||||
@@ -1,27 +0,0 @@
|
||||
from m5 import *
|
||||
from Device import BasicPioDevice
|
||||
from Platform import Platform
|
||||
|
||||
class Tsunami(Platform):
|
||||
type = 'Tsunami'
|
||||
# pciconfig = Param.PciConfigAll("PCI configuration")
|
||||
system = Param.System(Parent.any, "system")
|
||||
|
||||
class TsunamiCChip(BasicPioDevice):
|
||||
type = 'TsunamiCChip'
|
||||
tsunami = Param.Tsunami(Parent.any, "Tsunami")
|
||||
|
||||
class IsaFake(BasicPioDevice):
|
||||
type = 'IsaFake'
|
||||
pio_size = Param.Addr(0x8, "Size of address range")
|
||||
|
||||
class TsunamiIO(BasicPioDevice):
|
||||
type = 'TsunamiIO'
|
||||
time = Param.UInt64(1136073600,
|
||||
"System time to use (0 for actual time, default is 1/1/06)")
|
||||
tsunami = Param.Tsunami(Parent.any, "Tsunami")
|
||||
frequency = Param.Frequency('1024Hz', "frequency of interrupts")
|
||||
|
||||
class TsunamiPChip(BasicPioDevice):
|
||||
type = 'TsunamiPChip'
|
||||
tsunami = Param.Tsunami(Parent.any, "Tsunami")
|
||||
@@ -1,15 +0,0 @@
|
||||
from m5 import *
|
||||
from Device import BasicPioDevice
|
||||
|
||||
class Uart(BasicPioDevice):
|
||||
type = 'Uart'
|
||||
abstract = True
|
||||
sim_console = Param.SimConsole(Parent.any, "The console")
|
||||
|
||||
class Uart8250(Uart):
|
||||
type = 'Uart8250'
|
||||
|
||||
if build_env['ALPHA_TLASER']:
|
||||
class Uart8530(Uart):
|
||||
type = 'Uart8530'
|
||||
|
||||
@@ -1,152 +0,0 @@
|
||||
# Copyright (c) 2005 The Regents of The University of Michigan
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
# The SmartDict class fixes a couple of issues with using the content
|
||||
# of os.environ or similar dicts of strings as Python variables:
|
||||
#
|
||||
# 1) Undefined variables should return False rather than raising KeyError.
|
||||
#
|
||||
# 2) String values of 'False', '0', etc., should evaluate to False
|
||||
# (not just the empty string).
|
||||
#
|
||||
# #1 is solved by overriding __getitem__, and #2 is solved by using a
|
||||
# proxy class for values and overriding __nonzero__ on the proxy.
|
||||
# Everything else is just to (a) make proxies behave like normal
|
||||
# values otherwise, (b) make sure any dict operation returns a proxy
|
||||
# rather than a normal value, and (c) coerce values written to the
|
||||
# dict to be strings.
|
||||
|
||||
|
||||
from convert import *
|
||||
|
||||
class Variable(str):
|
||||
"""Intelligent proxy class for SmartDict. Variable will use the
|
||||
various convert functions to attempt to convert values to useable
|
||||
types"""
|
||||
def __int__(self):
|
||||
return toInteger(str(self))
|
||||
def __long__(self):
|
||||
return toLong(str(self))
|
||||
def __float__(self):
|
||||
return toFloat(str(self))
|
||||
def __nonzero__(self):
|
||||
return toBool(str(self))
|
||||
def convert(self, other):
|
||||
t = type(other)
|
||||
if t == bool:
|
||||
return bool(self)
|
||||
if t == int:
|
||||
return int(self)
|
||||
if t == long:
|
||||
return long(self)
|
||||
if t == float:
|
||||
return float(self)
|
||||
return str(self)
|
||||
def __lt__(self, other):
|
||||
return self.convert(other) < other
|
||||
def __le__(self, other):
|
||||
return self.convert(other) <= other
|
||||
def __eq__(self, other):
|
||||
return self.convert(other) == other
|
||||
def __ne__(self, other):
|
||||
return self.convert(other) != other
|
||||
def __gt__(self, other):
|
||||
return self.convert(other) > other
|
||||
def __ge__(self, other):
|
||||
return self.convert(other) >= other
|
||||
|
||||
def __add__(self, other):
|
||||
return self.convert(other) + other
|
||||
def __sub__(self, other):
|
||||
return self.convert(other) - other
|
||||
def __mul__(self, other):
|
||||
return self.convert(other) * other
|
||||
def __div__(self, other):
|
||||
return self.convert(other) / other
|
||||
def __truediv__(self, other):
|
||||
return self.convert(other) / other
|
||||
|
||||
def __radd__(self, other):
|
||||
return other + self.convert(other)
|
||||
def __rsub__(self, other):
|
||||
return other - self.convert(other)
|
||||
def __rmul__(self, other):
|
||||
return other * self.convert(other)
|
||||
def __rdiv__(self, other):
|
||||
return other / self.convert(other)
|
||||
def __rtruediv__(self, other):
|
||||
return other / self.convert(other)
|
||||
|
||||
class UndefinedVariable(object):
|
||||
"""Placeholder class to represent undefined variables. Will
|
||||
generally cause an exception whenever it is used, but evaluates to
|
||||
zero for boolean truth testing such as in an if statement"""
|
||||
def __nonzero__(self):
|
||||
return False
|
||||
|
||||
class SmartDict(dict):
|
||||
"""Dictionary class that holds strings, but intelligently converts
|
||||
those strings to other types depending on their usage"""
|
||||
|
||||
def __getitem__(self, key):
|
||||
"""returns a Variable proxy if the values exists in the database and
|
||||
returns an UndefinedVariable otherwise"""
|
||||
|
||||
if key in self:
|
||||
return Variable(dict.get(self, key))
|
||||
else:
|
||||
# Note that this does *not* change the contents of the dict,
|
||||
# so that even after we call env['foo'] we still get a
|
||||
# meaningful answer from "'foo' in env" (which
|
||||
# calls dict.__contains__, which we do not override).
|
||||
return UndefinedVariable()
|
||||
|
||||
def __setitem__(self, key, item):
|
||||
"""intercept the setting of any variable so that we always
|
||||
store strings in the dict"""
|
||||
dict.__setitem__(self, key, str(item))
|
||||
|
||||
def values(self):
|
||||
return [ Variable(v) for v in dict.values(self) ]
|
||||
|
||||
def itervalues(self):
|
||||
for value in dict.itervalues(self):
|
||||
yield Variable(value)
|
||||
|
||||
def items(self):
|
||||
return [ (k, Variable(v)) for k,v in dict.items(self) ]
|
||||
|
||||
def iteritems(self):
|
||||
for key,value in dict.iteritems(self):
|
||||
yield key, Variable(value)
|
||||
|
||||
def get(self, key, default='False'):
|
||||
return Variable(dict.get(self, key, str(default)))
|
||||
|
||||
def setdefault(self, key, default='False'):
|
||||
return Variable(dict.setdefault(self, key, str(default)))
|
||||
|
||||
__all__ = [ 'SmartDict' ]
|
||||
Reference in New Issue
Block a user