935ba67b4f
SConscript:
Comment out sinic for now... needs to be fixed to compile under newmem.
configs/test/SysPaths.py:
Fix paths.
configs/test/fs.py:
SimpleCPU -> AtomicSimpleCPU
Fix vmlinux path
cpu/simple/atomic.cc:
Fix suspendContext() so quiesce works.
Don't forget to checkForInterrupts().
cpu/simple/base.cc:
Minor fix to interrupt check code.
dev/ide_disk.hh:
Don't declare regStats() in header since it's not in
.cc file anymore (will need to add it back in when
stats are added back).
dev/io_device.cc:
Set packet dest to Packet::Broadcast.
dev/pciconfigall.cc:
Set PCI config packet result to Success.
python/m5/objects/Root.py:
Add debug object to Root so things like break_cycles
can be set from command line.
--HG--
extra : convert_revision : aa1c652fe589784e753e13ad9acb0cd5f3b6eafb
24 lines
896 B
Python
24 lines
896 B
Python
from m5 import *
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from Serialize import Serialize
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from Statistics import Statistics
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from Trace import Trace
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from ExeTrace import ExecutionTrace
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from Debug import Debug
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class Root(SimObject):
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type = 'Root'
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clock = Param.RootClock('200MHz', "tick frequency")
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max_tick = Param.Tick('0', "maximum simulation ticks (0 = infinite)")
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progress_interval = Param.Tick('0',
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"print a progress message every n ticks (0 = never)")
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output_file = Param.String('cout', "file to dump simulator output to")
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checkpoint = Param.String('', "checkpoint file to load")
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# stats = Param.Statistics(Statistics(), "statistics object")
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# trace = Param.Trace(Trace(), "trace object")
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# serialize = Param.Serialize(Serialize(), "checkpoint generation options")
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stats = Statistics()
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trace = Trace()
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exetrace = ExecutionTrace()
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serialize = Serialize()
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debug = Debug()
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