stdlib: Add a prebuilt MESI_Three_Level cache
The cache is modeled after an AMD EPYC cache, but not exactly like AMD EPYC cache. - K cores per core complex (CCD), each core has one private split L1, and one private L2. - K cores in the same CCD share 1 slice of L3 cache, which is not a victim cache. - There can be multiple CCDs, which communicate with each other via Cross-CCD router. The Cross-CCD rounter is also connected to directory controllers and dma controllers. - All links latency are set to 1. Change-Id: Ib64248bed9155b8e48e5158ffdeebf1f2d770754 Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71598 Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Hoa Nguyen
committed by
Bobby R. Bruce
Bobby R. Bruce
parent
872dc8bf59
commit
b9db0976ca
@@ -154,6 +154,18 @@ PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
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PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
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'gem5/components/cachehierarchies/ruby/caches/mesi_three_level/'
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'l3_cache.py')
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PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
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'gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/'
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'octopi.py')
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PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
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'gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/'
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'core_complex.py')
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PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
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'gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/'
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'octopi_network.py')
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PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
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'gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/'
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'ruby_network_components.py')
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PySource('gem5.components.cachehierarchies.ruby.caches.mi_example',
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'gem5/components/cachehierarchies/ruby/caches/mi_example/__init__.py')
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PySource('gem5.components.cachehierarchies.ruby.caches.mi_example',
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@@ -0,0 +1,25 @@
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# Copyright (c) 2022-2023 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
|
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# notice, this list of conditions and the following disclaimer in the
|
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
|
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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@@ -0,0 +1,245 @@
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# Copyright (c) 2022-2023 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from typing import List, Tuple
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from gem5.isas import ISA
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from gem5.components.boards.abstract_board import AbstractBoard
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from gem5.components.processors.abstract_core import AbstractCore
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from gem5.components.cachehierarchies.ruby.caches.mesi_three_level.l1_cache import (
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L1Cache,
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)
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from gem5.components.cachehierarchies.ruby.caches.mesi_three_level.l2_cache import (
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L2Cache,
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)
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from gem5.components.cachehierarchies.ruby.caches.mesi_three_level.l3_cache import (
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L3Cache,
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)
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from m5.objects import SubSystem, RubySequencer
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from .ruby_network_components import (
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RubyRouter,
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RubyExtLink,
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RubyIntLink,
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RubyNetworkComponent,
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)
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class CoreComplex(SubSystem, RubyNetworkComponent):
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_core_id = 0
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_core_complex_id = 0
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@classmethod
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def _get_core_id(cls):
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cls._core_id += 1
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return cls._core_id - 1
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@classmethod
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def _get_core_complex_id(cls):
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cls._core_complex_id += 1
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return cls._core_complex_id - 1
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def __init__(
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self,
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board: AbstractBoard,
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cores: List[AbstractCore],
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ruby_system,
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l1i_size: str,
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l1i_assoc: int,
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l1d_size: str,
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l1d_assoc: int,
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l2_size: str,
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l2_assoc: int,
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l3_size: str,
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l3_assoc: int,
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):
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SubSystem.__init__(self=self)
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RubyNetworkComponent.__init__(self=self)
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self._l1i_size = l1i_size
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self._l1i_assoc = l1i_assoc
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self._l1d_size = l1d_size
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self._l1d_assoc = l1d_assoc
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self._l2_size = l2_size
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self._l2_assoc = l2_assoc
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self._l3_size = l3_size
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self._l3_assoc = l3_assoc
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self._board = board
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self._cores = cores
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self._ruby_system = ruby_system
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self._cache_line_size = 64
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self._directory_controllers = []
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self._core_complex_id = self._get_core_complex_id()
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self.main_router = RubyRouter(
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self._ruby_system
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) # this will be connect to component outside the core complex
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self._add_router(self.main_router)
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self._create_core_complex()
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def get_main_router(self):
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return self.main_router
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def _create_core_complex(self):
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# Create L1 caches, L2 cache, and corresponding controllers per core
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self.core_clusters = [
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self._create_core_cluster(core) for core in self._cores
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]
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# Create L3 cache and its corresponding controller
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self._create_shared_cache()
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# Setting up one router and one external link per controller
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self._create_external_links()
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# Setting up L1/L2 links, L2/main links, L3/main link
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self._create_internal_links()
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def _create_core_cluster(self, core: AbstractCore):
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cluster = SubSystem()
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core_id = self._get_core_id()
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cluster.l1_cache = L1Cache(
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l1i_size=self._l1i_size,
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l1i_assoc=self._l1i_assoc,
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l1d_size=self._l1d_size,
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l1d_assoc=self._l1d_assoc,
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network=self._ruby_system.network,
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core=core,
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cache_line_size=self._cache_line_size,
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target_isa=self._board.processor.get_isa(),
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clk_domain=self._board.get_clock_domain(),
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)
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cluster.l1_cache.sequencer = RubySequencer(
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version=core_id,
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dcache=cluster.l1_cache.Dcache,
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clk_domain=cluster.l1_cache.clk_domain,
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)
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if self._board.has_io_bus():
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cluster.l1_cache.sequencer.connectIOPorts(self._board.get_io_bus())
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cluster.l1_cache.ruby_system = self._ruby_system
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core.connect_icache(cluster.l1_cache.sequencer.in_ports)
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core.connect_dcache(cluster.l1_cache.sequencer.in_ports)
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core.connect_walker_ports(
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cluster.l1_cache.sequencer.in_ports,
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cluster.l1_cache.sequencer.in_ports,
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)
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if self._board.get_processor().get_isa() == ISA.X86:
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core.connect_interrupt(
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cluster.l1_cache.sequencer.interrupt_out_port,
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cluster.l1_cache.sequencer.in_ports,
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)
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else:
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core.connect_interrupt()
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cluster.l2_cache = L2Cache(
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l2_size=self._l2_size,
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l2_assoc=self._l2_assoc,
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network=self._ruby_system.network,
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core=core,
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num_l3Caches=1, # each core complex has 1 slice of L3 Cache
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cache_line_size=self._cache_line_size,
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cluster_id=self._core_complex_id,
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target_isa=self._board.processor.get_isa(),
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clk_domain=self._board.get_clock_domain(),
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)
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cluster.l2_cache.ruby_system = self._ruby_system
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# L0Cache in the ruby backend is l1 cache in stdlib
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# L1Cache in the ruby backend is l2 cache in stdlib
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cluster.l2_cache.bufferFromL0 = cluster.l1_cache.bufferToL1
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cluster.l2_cache.bufferToL0 = cluster.l1_cache.bufferFromL1
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return cluster
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def _create_shared_cache(self):
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self.l3_cache = L3Cache(
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l3_size=self._l3_size,
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l3_assoc=self._l3_assoc,
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network=self._ruby_system.network,
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num_l3Caches=1,
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cache_line_size=self._cache_line_size,
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cluster_id=self._core_complex_id,
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)
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self.l3_cache.ruby_system = self._ruby_system
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# This is where all routers and links are created
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def _create_external_links(self):
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# create a router per cache controller
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# - there is one L3 per ccd
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self.l3_router = RubyRouter(self._ruby_system)
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self._add_router(self.l3_router)
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# - there is one L1 and one L2 per cluster
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for cluster in self.core_clusters:
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cluster.l1_router = RubyRouter(self._ruby_system)
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self._add_router(cluster.l1_router)
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cluster.l2_router = RubyRouter(self._ruby_system)
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self._add_router(cluster.l2_router)
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# create an ext link from a controller to a router
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self.l3_router_link = RubyExtLink(
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ext_node=self.l3_cache,
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int_node=self.l3_router,
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bandwidth_factor=64,
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)
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self._add_ext_link(self.l3_router_link)
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for cluster in self.core_clusters:
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cluster.l1_router_link = RubyExtLink(
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ext_node=cluster.l1_cache, int_node=cluster.l1_router
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)
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self._add_ext_link(cluster.l1_router_link)
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cluster.l2_router_link = RubyExtLink(
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ext_node=cluster.l2_cache, int_node=cluster.l2_router
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)
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self._add_ext_link(cluster.l2_router_link)
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def _create_internal_links(self):
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# create L1/L2 links
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for cluster in self.core_clusters:
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l1_to_l2, l2_to_l1 = RubyIntLink.create_bidirectional_links(
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cluster.l1_router, cluster.l2_router
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)
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cluster.l1_to_l2_link = l1_to_l2
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cluster.l2_to_l1_link = l2_to_l1
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self._add_int_link(l1_to_l2)
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self._add_int_link(l2_to_l1)
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# create L2/main_router links
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for cluster in self.core_clusters:
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l2_to_main, main_to_l2 = RubyIntLink.create_bidirectional_links(
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cluster.l2_router, self.main_router
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)
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cluster.l2_to_main_link = l2_to_main
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cluster.main_to_l2_link = main_to_l2
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self._add_int_link(l2_to_main)
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self._add_int_link(main_to_l2)
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# create L3/main_router link
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l3_to_main, main_to_l3 = RubyIntLink.create_bidirectional_links(
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self.l3_router, self.main_router, bandwidth_factor=64
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)
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self.l3_to_main_link = l3_to_main
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self.main_to_l3_link = main_to_l3
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self._add_int_link(l3_to_main)
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self._add_int_link(main_to_l3)
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@@ -0,0 +1,257 @@
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# Copyright (c) 2022-2023 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
|
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# modification, are permitted provided that the following conditions are
|
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# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
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# documentation and/or other materials provided with the distribution;
|
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# neither the name of the copyright holders nor the names of its
|
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# contributors may be used to endorse or promote products derived from
|
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# this software without specific prior written permission.
|
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#
|
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from ...abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy
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from ....abstract_three_level_cache_hierarchy import (
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AbstractThreeLevelCacheHierarchy,
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)
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from ......coherence_protocol import CoherenceProtocol
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from ......components.boards.abstract_board import AbstractBoard
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from ......utils.requires import requires
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from ......components.cachehierarchies.ruby.caches.mesi_three_level.directory import (
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Directory,
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)
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from ......components.cachehierarchies.ruby.caches.mesi_three_level.dma_controller import (
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DMAController,
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)
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from m5.objects import RubySystem, DMASequencer, RubyPortProxy
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from .core_complex import CoreComplex
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from .octopi_network import OctopiNetwork
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from .ruby_network_components import RubyRouter, RubyExtLink, RubyIntLink
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# CoreComplex sub-systems own the L1, L2, L3 controllers
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# OctopiCache owns the directory controllers
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# RubySystem owns the DMA Controllers
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class OctopiCache(
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AbstractRubyCacheHierarchy, AbstractThreeLevelCacheHierarchy
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):
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def __init__(
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self,
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l1i_size: str,
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l1i_assoc: int,
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l1d_size: str,
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l1d_assoc: int,
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l2_size: str,
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l2_assoc: int,
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l3_size: str,
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l3_assoc: int,
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num_core_complexes: int,
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is_fullsystem: bool,
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):
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AbstractRubyCacheHierarchy.__init__(self=self)
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AbstractThreeLevelCacheHierarchy.__init__(
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self=self,
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l1i_size=l1i_size,
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l1i_assoc=l1i_assoc,
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l1d_size=l1d_size,
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l1d_assoc=l1d_assoc,
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l2_size=l2_size,
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l2_assoc=l2_assoc,
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l3_size=l3_size,
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l3_assoc=l3_assoc,
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)
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self._directory_controllers = []
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self._dma_controllers = []
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self._io_controllers = []
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self._core_complexes = []
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self._num_core_complexes = num_core_complexes
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self._is_fullsystem = is_fullsystem
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def incorporate_cache(self, board: AbstractBoard) -> None:
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requires(
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coherence_protocol_required=CoherenceProtocol.MESI_THREE_LEVEL
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)
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cache_line_size = board.get_cache_line_size()
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self.ruby_system = RubySystem()
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# MESI_Three_Level needs 3 virtual networks
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self.ruby_system.number_of_virtual_networks = 3
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self.ruby_system.network = OctopiNetwork(self.ruby_system)
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# Setting up the core complex
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all_cores = board.get_processor().get_cores()
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num_cores_per_core_complex = len(all_cores) // self._num_core_complexes
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self.core_complexes = [
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CoreComplex(
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board=board,
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cores=all_cores[
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core_complex_idx
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* num_cores_per_core_complex : (core_complex_idx + 1)
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* num_cores_per_core_complex
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],
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ruby_system=self.ruby_system,
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l1i_size=self._l1i_size,
|
||||
l1i_assoc=self._l1i_assoc,
|
||||
l1d_size=self._l1d_size,
|
||||
l1d_assoc=self._l1d_assoc,
|
||||
l2_size=self._l2_size,
|
||||
l2_assoc=self._l2_assoc,
|
||||
l3_size=self._l3_size,
|
||||
l3_assoc=self._l3_assoc,
|
||||
)
|
||||
for core_complex_idx in range(self._num_core_complexes)
|
||||
]
|
||||
|
||||
self.ruby_system.network.incorporate_ccds(self.core_complexes)
|
||||
|
||||
self._create_directory_controllers(board)
|
||||
self._create_dma_controllers(board, self.ruby_system)
|
||||
|
||||
self.ruby_system.num_of_sequencers = (
|
||||
len(all_cores)
|
||||
+ len(self._dma_controllers)
|
||||
+ len(self._io_controllers)
|
||||
)
|
||||
# SimpleNetwork requires .int_links and .routers to exist
|
||||
# if we want to call SimpleNetwork.setup_buffers()
|
||||
self.ruby_system.network.int_links = (
|
||||
self.ruby_system.network._int_links
|
||||
)
|
||||
self.ruby_system.network.ext_links = (
|
||||
self.ruby_system.network._ext_links
|
||||
)
|
||||
self.ruby_system.network.routers = self.ruby_system.network._routers
|
||||
self.ruby_system.network.setup_buffers()
|
||||
|
||||
# Set up a proxy port for the system_port. Used for load binaries and
|
||||
# other functional-only things.
|
||||
self.ruby_system.sys_port_proxy = RubyPortProxy()
|
||||
board.connect_system_port(self.ruby_system.sys_port_proxy.in_ports)
|
||||
|
||||
def _create_directory_controllers(self, board):
|
||||
# Adding controllers
|
||||
self.directory_controllers = [
|
||||
Directory(
|
||||
self.ruby_system.network,
|
||||
board.get_cache_line_size(),
|
||||
addr_range,
|
||||
mem_port,
|
||||
)
|
||||
for addr_range, mem_port in board.get_mem_ports()
|
||||
]
|
||||
for ctrl in self.directory_controllers:
|
||||
ctrl.ruby_system = self.ruby_system
|
||||
# Adding controller routers
|
||||
self.directory_controller_routers = [
|
||||
RubyRouter(self.ruby_system.network)
|
||||
for _ in range(len(self.directory_controllers))
|
||||
]
|
||||
for router in self.directory_controller_routers:
|
||||
self.ruby_system.network._add_router(router)
|
||||
# Adding an external link for each controller and its router
|
||||
self.directory_controller_ext_links = [
|
||||
RubyExtLink(ext_node=dir_ctrl, int_node=dir_router)
|
||||
for dir_ctrl, dir_router in zip(
|
||||
self.directory_controllers, self.directory_controller_routers
|
||||
)
|
||||
]
|
||||
for ext_link in self.directory_controller_ext_links:
|
||||
self.ruby_system.network._add_ext_link(ext_link)
|
||||
_directory_controller_int_links = []
|
||||
for router in self.directory_controller_routers:
|
||||
int_link_1, int_link_2 = RubyIntLink.create_bidirectional_links(
|
||||
router, self.ruby_system.network.cross_ccd_router
|
||||
)
|
||||
_directory_controller_int_links.extend([int_link_1, int_link_2])
|
||||
self.ruby_system.network._add_int_link(int_link_1)
|
||||
self.ruby_system.network._add_int_link(int_link_2)
|
||||
self.directory_controller_int_links = _directory_controller_int_links
|
||||
|
||||
def _create_dma_controllers(self, board, ruby_system):
|
||||
# IOController for full system simulation
|
||||
if self._is_fullsystem:
|
||||
self.io_sequencer = DMASequencer(
|
||||
version=0, ruby_system=self.ruby_system
|
||||
)
|
||||
self.io_sequencer.in_ports = board.get_mem_side_coherent_io_port()
|
||||
self.ruby_system.io_controller = DMAController(
|
||||
dma_sequencer=self.io_sequencer, ruby_system=self.ruby_system
|
||||
)
|
||||
self._io_controllers.append(self.ruby_system.io_controller)
|
||||
self.io_controller_router = RubyRouter(self.ruby_system.network)
|
||||
self.ruby_system.network._add_router(self.io_controller_router)
|
||||
self.io_controller_ext_link = RubyExtLink(
|
||||
ext_node=self._io_controllers[0],
|
||||
int_node=self.io_controller_router,
|
||||
)
|
||||
self.ruby_system.network._add_ext_link(self.io_controller_ext_link)
|
||||
self.io_controller_int_links = (
|
||||
RubyIntLink.create_bidirectional_links(
|
||||
self.io_controller_router,
|
||||
self.ruby_system.network.cross_ccd_router,
|
||||
)
|
||||
)
|
||||
self.ruby_system.network._add_int_link(
|
||||
self.io_controller_int_links[0]
|
||||
)
|
||||
self.ruby_system.network._add_int_link(
|
||||
self.io_controller_int_links[1]
|
||||
)
|
||||
|
||||
self._dma_controllers = []
|
||||
if board.has_dma_ports():
|
||||
self.ruby_system.dma_controllers = [
|
||||
DMAController(
|
||||
dma_sequencer=DMASequencer(version=i + 1, in_ports=port),
|
||||
ruby_system=self.ruby_system,
|
||||
)
|
||||
for i, port in enumerate(board.get_dma_ports())
|
||||
]
|
||||
self._dma_controllers = self.ruby_system.dma_controllers
|
||||
self.dma_routers = [
|
||||
RubyRouter(self.ruby_system.network)
|
||||
for dma_controller in self._dma_controllers
|
||||
]
|
||||
for dma_router in self.dma_routers:
|
||||
self.ruby_system.network._add_router(dma_router)
|
||||
self.dma_ext_links = [
|
||||
RubyExtLink(ext_node=dma_controller, int_node=dma_router)
|
||||
for dma_controller, dma_router in zip(
|
||||
self._dma_controllers, self.dma_routers
|
||||
)
|
||||
]
|
||||
for link in self.dma_ext_links:
|
||||
self.ruby_system.network._add_ext_link(link)
|
||||
self.dma_int_links = [
|
||||
RubyIntLink(
|
||||
dma_router, self.ruby_system.network.cross_ccd_router
|
||||
)
|
||||
for dma_router in self.dma_routers
|
||||
] + [
|
||||
RubyIntLink(
|
||||
self.ruby_system.network.cross_ccd_router, dma_router
|
||||
)
|
||||
for dma_router in self.dma_routers
|
||||
]
|
||||
for link in self.dma_int_links:
|
||||
self.ruby_system.network._add_int_link(link)
|
||||
@@ -0,0 +1,67 @@
|
||||
# Copyright (c) 2022-2023 The Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
from m5.objects import SimpleNetwork
|
||||
|
||||
from .ruby_network_components import (
|
||||
RubyNetworkComponent,
|
||||
RubyRouter,
|
||||
RubyIntLink,
|
||||
)
|
||||
|
||||
# . The Network owns all routers, all int links and all ext links that are not in CCD's.
|
||||
# . The CCD subsystems are not of type RubyNetwork, so we need to copy the references of
|
||||
# routers and links to OctopiNetwork._routers, ._int_links, and ._ext_links; which will
|
||||
# be, in turns, copied to RubyNetwork.routers, .int_links, and .ext_links respectively.
|
||||
class OctopiNetwork(SimpleNetwork, RubyNetworkComponent):
|
||||
def __init__(self, ruby_system):
|
||||
SimpleNetwork.__init__(self=self)
|
||||
RubyNetworkComponent.__init__(self=self)
|
||||
self.netifs = []
|
||||
self.ruby_system = ruby_system
|
||||
self.number_of_virtual_networks = (
|
||||
ruby_system.number_of_virtual_networks
|
||||
)
|
||||
|
||||
self.cross_ccd_router = RubyRouter(self)
|
||||
self._add_router(self.cross_ccd_router)
|
||||
|
||||
def connect_ccd_routers_to_cross_ccd_router(self, ccds):
|
||||
for ccd in ccds:
|
||||
int_link_1, int_link_2 = RubyIntLink.create_bidirectional_links(
|
||||
self.cross_ccd_router,
|
||||
ccd.get_main_router(),
|
||||
bandwidth_factor=64,
|
||||
)
|
||||
ccd.to_cross_ccd_router_link = int_link_1
|
||||
ccd.from_cross_ccd_router_link = int_link_2
|
||||
self._add_int_link(int_link_1)
|
||||
self._add_int_link(int_link_2)
|
||||
|
||||
def incorporate_ccds(self, ccds):
|
||||
for ccd in ccds:
|
||||
self.incorporate_ruby_subsystem(ccd)
|
||||
self.connect_ccd_routers_to_cross_ccd_router(ccds)
|
||||
@@ -0,0 +1,111 @@
|
||||
# Copyright (c) 2022-2023 The Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
from m5.objects import Switch, SimpleIntLink, SimpleExtLink
|
||||
|
||||
|
||||
class RubyNetworkComponent:
|
||||
def __init__(self):
|
||||
super().__init__()
|
||||
self._routers = []
|
||||
self._ext_links = []
|
||||
self._int_links = []
|
||||
|
||||
def _add_router(self, router):
|
||||
self._routers.append(router)
|
||||
|
||||
def _add_ext_link(self, link):
|
||||
self._ext_links.append(link)
|
||||
|
||||
def _add_int_link(self, link):
|
||||
self._int_links.append(link)
|
||||
|
||||
def get_routers(self):
|
||||
return self._routers
|
||||
|
||||
def get_ext_links(self):
|
||||
return self._ext_links
|
||||
|
||||
def get_int_links(self):
|
||||
return self._int_links
|
||||
|
||||
def incorporate_ruby_subsystem(self, other_ruby_subsystem):
|
||||
self._routers.extend(other_ruby_subsystem.get_routers())
|
||||
self._ext_links.extend(other_ruby_subsystem.get_ext_links())
|
||||
self._int_links.extend(other_ruby_subsystem.get_int_links())
|
||||
|
||||
|
||||
class RubyRouter(Switch):
|
||||
_router_id = 0
|
||||
|
||||
@classmethod
|
||||
def _get_router_id(cls):
|
||||
cls._router_id += 1
|
||||
return cls._router_id - 1
|
||||
|
||||
def __init__(self, network):
|
||||
super().__init__()
|
||||
self.router_id = self._get_router_id()
|
||||
self.virt_nets = network.number_of_virtual_networks
|
||||
|
||||
|
||||
class RubyExtLink(SimpleExtLink):
|
||||
_link_id = 0
|
||||
|
||||
@classmethod
|
||||
def _get_link_id(cls):
|
||||
cls._link_id += 1
|
||||
return cls._link_id - 1
|
||||
|
||||
def __init__(self, ext_node, int_node, bandwidth_factor=16):
|
||||
super().__init__()
|
||||
self.link_id = self._get_link_id()
|
||||
self.ext_node = ext_node
|
||||
self.int_node = int_node
|
||||
self.bandwidth_factor = bandwidth_factor
|
||||
|
||||
|
||||
class RubyIntLink(SimpleIntLink):
|
||||
_link_id = 0
|
||||
|
||||
@classmethod
|
||||
def _get_link_id(cls):
|
||||
cls._link_id += 1
|
||||
return cls._link_id - 1
|
||||
|
||||
@classmethod
|
||||
def create_bidirectional_links(cls, node_1, node_2, bandwidth_factor=16):
|
||||
return [
|
||||
RubyIntLink(node_1, node_2, bandwidth_factor),
|
||||
RubyIntLink(node_2, node_1, bandwidth_factor),
|
||||
]
|
||||
|
||||
def __init__(self, src_node, dst_node, bandwidth_factor=16):
|
||||
super().__init__()
|
||||
self.link_id = self._get_link_id()
|
||||
self.src_node = src_node
|
||||
self.dst_node = dst_node
|
||||
self.bandwidth_factor = bandwidth_factor
|
||||
Reference in New Issue
Block a user