ARM: Add support for DIV/SDIV instructions.
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@@ -140,7 +140,7 @@ ISA::clear()
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// See section B4.1.84 of ARM ARM
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// All values are latest for ARMv7-A profile
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miscRegs[MISCREG_ID_ISAR0] = 0x01101111;
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miscRegs[MISCREG_ID_ISAR0] = 0x02101111;
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miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
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miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
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miscRegs[MISCREG_ID_ISAR3] = 0x01112131;
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@@ -394,6 +394,16 @@ def format ArmSignedMultiplies() {{
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}
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}
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break;
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case 0x1:
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if (op2 == 0 && m == 0 && ra == 0xf) {
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return new Sdiv(machInst, rd, rn, rm);
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}
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break;
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case 0x3:
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if (op2 == 0 && m == 0 && ra == 0xf) {
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return new Udiv(machInst, rd, rn, rm);
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}
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break;
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case 0x4:
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if (op2 == 0) {
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if (m) {
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