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arch-vega: Improve disasm for GLOBAL insts with scalar offset

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The previous print statement was not clear that a scalar offset was
being used when printing disassembly, which made it slightly more
difficult to track down bugs related to this (relatively) rare usage of
global load/store instructions.

This change improves the disassembly to closer match the output of
hipcc's assembly code output.

Change-Id: I8514aedacb5b1db93d0586c408c4cf1ce77a7db3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63175
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
This commit is contained in:
Matthew Poremba
2022-09-05 10:27:55 -07:00
parent 6c935657fd
commit b919d9c5c9
1 changed files with 9 additions and 2 deletions
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11
src/arch/amdgpu/vega/insts/op_encodings.cc
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@@ -1732,7 +1732,10 @@ namespace VegaISA
if (isLoad())
dis_stream << "v" << extData.VDST << ", ";
dis_stream << "v[" << extData.ADDR << ":" << extData.ADDR + 1 << "]";
if (extData.SADDR == 0x7f)
dis_stream << "v[" << extData.ADDR << ":" << extData.ADDR+1 << "]";
else
dis_stream << "v" << extData.ADDR;
if (isStore())
dis_stream << ", v" << extData.DATA;
@@ -1740,7 +1743,11 @@ namespace VegaISA
if (extData.SADDR == 0x7f)
dis_stream << ", off";
else
dis_stream << ", " << extData.SADDR;
dis_stream << ", s[" << extData.SADDR << ":" << extData.SADDR+1
<< "]";
if (instData.OFFSET)
dis_stream << " offset:" << instData.OFFSET;
disassembly = dis_stream.str();
}