derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-arm: De-macrofy arch/arm/kvm/arm_cpu.cc.

Browse Source 
Replace macros with inline functions.

Change-Id: I26571959152aed5f62c543e62750e564fe27bf28
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45879
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-05-22 19:43:16 -07:00
parent 8fee59a9af
commit b783a62fb8
1 changed files with 331 additions and 242 deletions
Download Patch File Download Diff File Expand all files Collapse all files

573
src/arch/arm/kvm/arm_cpu.cc
View File

@@ -42,6 +42,7 @@
#include <algorithm>
#include <cerrno>
#include <memory>
#include <set>
#include "arch/arm/interrupts.hh"
#include "arch/arm/regs/int.hh"
@@ -54,193 +55,284 @@
using namespace ArmISA;
#define EXTRACT_FIELD(val, mask, shift) \
(((val) & (mask)) >> (shift))
namespace
{
#define REG_IS_ARM(id) \
(((id) & KVM_REG_ARCH_MASK) == KVM_REG_ARM)
constexpr uint64_t
extractField(uint64_t val, uint64_t mask, size_t shift)
{
return (val & mask) >> shift;
}
#define REG_IS_32BIT(id) \
(((id) & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32)
constexpr bool
regIsArm(uint64_t id)
{
return (id & KVM_REG_ARCH_MASK) == KVM_REG_ARM;
}
#define REG_IS_64BIT(id) \
(((id) & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64)
constexpr bool
regIs32Bit(uint64_t id)
{
return (id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32;
}
#define REG_IS_CP(id, cp) \
(((id) & KVM_REG_ARM_COPROC_MASK) == (cp))
constexpr bool
regIs64Bit(uint64_t id)
{
return (id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64;
}
#define REG_IS_CORE(id) REG_IS_CP((id), KVM_REG_ARM_CORE)
constexpr bool
regIsCp(uint64_t id, uint64_t cp)
{
return (id & KVM_REG_ARM_COPROC_MASK) == cp;
}
constexpr bool
regIsCore(uint64_t id)
{
return regIsCp(id, KVM_REG_ARM_CORE);
}
constexpr bool
regIsVfp(uint64_t id)
{
return regIsCp(id, KVM_REG_ARM_VFP);
}
constexpr uint64_t
regVfpReg(uint64_t id)
{
return id & KVM_REG_ARM_VFP_MASK;
}
#define REG_IS_VFP(id) REG_IS_CP((id), KVM_REG_ARM_VFP)
#define REG_VFP_REG(id) ((id) & KVM_REG_ARM_VFP_MASK)
// HACK: These aren't really defined in any of the headers, so we'll
// assume some reasonable values for now.
#define REG_IS_VFP_REG(id) (REG_VFP_REG(id) < 0x100)
#define REG_IS_VFP_CTRL(id) (REG_VFP_REG(id) >= 0x100)
constexpr bool
regIsVfpReg(uint64_t id)
{
return regVfpReg(id) < 0x100;
}
constexpr bool
regIsVfpCtrl(uint64_t id)
{
return regVfpReg(id) >= 0x100;
}
#define REG_IS_DEMUX(id) REG_IS_CP((id), KVM_REG_ARM_DEMUX)
constexpr bool
regIsDemux(uint64_t id)
{
return regIsCp(id, KVM_REG_ARM_DEMUX);
}
// There is no constant in the kernel headers defining the mask to use
// to get the core register index. We'll just do what they do
// internally.
#define REG_CORE_IDX(id) \
(~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE))
constexpr uint64_t
regCoreIdx(uint64_t id)
{
return ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE);
}
#define REG_CP(id) \
EXTRACT_FIELD(id, KVM_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_SHIFT)
constexpr uint64_t
regCp(uint64_t id)
{
return extractField(id, KVM_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_SHIFT);
}
#define REG_CRN(id) \
EXTRACT_FIELD(id, KVM_REG_ARM_32_CRN_MASK, KVM_REG_ARM_32_CRN_SHIFT)
constexpr uint64_t
regCrn(uint64_t id)
{
return extractField(id, KVM_REG_ARM_32_CRN_MASK, KVM_REG_ARM_32_CRN_SHIFT);
}
#define REG_OPC1(id) \
EXTRACT_FIELD(id, KVM_REG_ARM_OPC1_MASK, KVM_REG_ARM_OPC1_SHIFT)
constexpr uint64_t
regOpc1(uint64_t id)
{
return extractField(id, KVM_REG_ARM_OPC1_MASK, KVM_REG_ARM_OPC1_SHIFT);
}
#define REG_CRM(id) \
EXTRACT_FIELD(id, KVM_REG_ARM_CRM_MASK, KVM_REG_ARM_CRM_SHIFT)
constexpr uint64_t
regCrm(uint64_t id)
{
return extractField(id, KVM_REG_ARM_CRM_MASK, KVM_REG_ARM_CRM_SHIFT);
}
#define REG_OPC2(id) \
EXTRACT_FIELD(id, KVM_REG_ARM_32_OPC2_MASK, KVM_REG_ARM_32_OPC2_SHIFT)
constexpr uint64_t
regOpc2(uint64_t id)
{
return extractField(id, KVM_REG_ARM_32_OPC2_MASK,
KVM_REG_ARM_32_OPC2_SHIFT);
}
#define REG_CP32(cpnum, crn, opc1, crm, opc2) ( \
(KVM_REG_ARM | KVM_REG_SIZE_U32) | \
((cpnum) << KVM_REG_ARM_COPROC_SHIFT) | \
((crn) << KVM_REG_ARM_32_CRN_SHIFT) | \
((opc1) << KVM_REG_ARM_OPC1_SHIFT) | \
((crm) << KVM_REG_ARM_CRM_SHIFT) | \
((opc2) << KVM_REG_ARM_32_OPC2_SHIFT))
constexpr uint64_t
regCp32(uint64_t cpnum, uint64_t crn, uint64_t opc1, uint64_t crm,
uint64_t opc2)
{
return KVM_REG_ARM | KVM_REG_SIZE_U32 |
(cpnum << KVM_REG_ARM_COPROC_SHIFT) |
(crn << KVM_REG_ARM_32_CRN_SHIFT) |
(opc1 << KVM_REG_ARM_OPC1_SHIFT) |
(crm << KVM_REG_ARM_CRM_SHIFT) |
(opc2 << KVM_REG_ARM_32_OPC2_SHIFT);
}
#define REG_CP64(cpnum, opc1, crm) ( \
(KVM_REG_ARM | KVM_REG_SIZE_U64) | \
((cpnum) << KVM_REG_ARM_COPROC_SHIFT) | \
((opc1) << KVM_REG_ARM_OPC1_SHIFT) | \
((crm) << KVM_REG_ARM_CRM_SHIFT))
constexpr uint64_t
regCp64(uint64_t cpnum, uint64_t opc1, uint64_t crm)
{
return KVM_REG_ARM | KVM_REG_SIZE_U64 |
(cpnum << KVM_REG_ARM_COPROC_SHIFT) |
(opc1 << KVM_REG_ARM_OPC1_SHIFT) |
(crm << KVM_REG_ARM_CRM_SHIFT);
}
#define REG_CORE32(kname) ( \
(KVM_REG_ARM | KVM_REG_SIZE_U32) | \
(KVM_REG_ARM_CORE) | \
(KVM_REG_ARM_CORE_REG(kname)))
constexpr KvmIntRegInfo
regCore32(off_t offset, ArmISA::IntRegIndex idx, const char *name)
{
return { KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_CORE | offset,
idx, name };
}
#define REG_VFP32(regno) ( \
(KVM_REG_ARM | KVM_REG_SIZE_U32) | \
KVM_REG_ARM_VFP | (regno))
constexpr uint64_t
regVfp32(uint64_t regno)
{
return KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | regno;
}
#define REG_VFP64(regno) ( \
(KVM_REG_ARM | KVM_REG_SIZE_U64) | \
KVM_REG_ARM_VFP | (regno))
constexpr uint64_t
regVfp64(uint64_t regno)
{
return KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | regno;
}
#define REG_DEMUX32(dmxid, val) ( \
(KVM_REG_ARM | KVM_REG_SIZE_U32) | \
(dmxid) | (val))
constexpr uint64_t
regDemux32(uint64_t dmxid, uint64_t val)
{
return KVM_REG_ARM | KVM_REG_SIZE_U32 | dmxid | val;
}
constexpr uint64_t
interruptId(uint64_t type, uint64_t vcpu, uint64_t irq)
{
return (type << KVM_ARM_IRQ_TYPE_SHIFT) |
(vcpu << KVM_ARM_IRQ_VCPU_SHIFT) |
(irq << KVM_ARM_IRQ_NUM_SHIFT);
}
constexpr uint64_t
interruptVcpuIrq(uint64_t vcpu)
{
return interruptId(KVM_ARM_IRQ_TYPE_CPU, vcpu, KVM_ARM_IRQ_CPU_IRQ);
}
constexpr uint64_t
interruptVcpuFiq(uint64_t vcpu)
{
return interruptId(KVM_ARM_IRQ_TYPE_CPU, vcpu, KVM_ARM_IRQ_CPU_FIQ);
}
} // anonymous namespace
// Some of the co-processor registers are invariants and must have the
// same value on both the host and the guest. We need to keep a list
// of these to prevent gem5 from fiddling with them on the guest.
static uint64_t invariant_reg_vector[] = {
REG_CP32(15, 0, 0, 0, 0), // MIDR
REG_CP32(15, 0, 0, 0, 1), // CTR
REG_CP32(15, 0, 0, 0, 2), // TCMTR
REG_CP32(15, 0, 0, 0, 3), // TLBTR
REG_CP32(15, 0, 0, 0, 6), // REVIDR
regCp32(15, 0, 0, 0, 0), // MIDR
regCp32(15, 0, 0, 0, 1), // CTR
regCp32(15, 0, 0, 0, 2), // TCMTR
regCp32(15, 0, 0, 0, 3), // TLBTR
regCp32(15, 0, 0, 0, 6), // REVIDR
REG_CP32(15, 0, 0, 1, 0), // ID_PFR0
REG_CP32(15, 0, 0, 1, 1), // ID_PFR1
REG_CP32(15, 0, 0, 1, 2), // ID_DFR0
REG_CP32(15, 0, 0, 1, 3), // ID_AFR0
REG_CP32(15, 0, 0, 1, 4), // ID_MMFR0
REG_CP32(15, 0, 0, 1, 5), // ID_MMFR1
REG_CP32(15, 0, 0, 1, 6), // ID_MMFR2
REG_CP32(15, 0, 0, 1, 7), // ID_MMFR3
regCp32(15, 0, 0, 1, 0), // ID_PFR0
regCp32(15, 0, 0, 1, 1), // ID_PFR1
regCp32(15, 0, 0, 1, 2), // ID_DFR0
regCp32(15, 0, 0, 1, 3), // ID_AFR0
regCp32(15, 0, 0, 1, 4), // ID_MMFR0
regCp32(15, 0, 0, 1, 5), // ID_MMFR1
regCp32(15, 0, 0, 1, 6), // ID_MMFR2
regCp32(15, 0, 0, 1, 7), // ID_MMFR3
REG_CP32(15, 0, 0, 2, 0), // ID_ISAR0
REG_CP32(15, 0, 0, 2, 1), // ID_ISAR1
REG_CP32(15, 0, 0, 2, 2), // ID_ISAR2
REG_CP32(15, 0, 0, 2, 3), // ID_ISAR3
REG_CP32(15, 0, 0, 2, 4), // ID_ISAR4
REG_CP32(15, 0, 0, 2, 5), // ID_ISAR5
REG_CP32(15, 0, 0, 2, 6), // ID_MMFR4
REG_CP32(15, 0, 0, 2, 7), // ID_ISAR6
regCp32(15, 0, 0, 2, 0), // ID_ISAR0
regCp32(15, 0, 0, 2, 1), // ID_ISAR1
regCp32(15, 0, 0, 2, 2), // ID_ISAR2
regCp32(15, 0, 0, 2, 3), // ID_ISAR3
regCp32(15, 0, 0, 2, 4), // ID_ISAR4
regCp32(15, 0, 0, 2, 5), // ID_ISAR5
regCp32(15, 0, 0, 2, 6), // ID_MMFR4
regCp32(15, 0, 0, 2, 7), // ID_ISAR6
REG_CP32(15, 0, 1, 0, 0), // CSSIDR
REG_CP32(15, 0, 1, 0, 1), // CLIDR
REG_CP32(15, 0, 1, 0, 7), // AIDR
regCp32(15, 0, 1, 0, 0), // CSSIDR
regCp32(15, 0, 1, 0, 1), // CLIDR
regCp32(15, 0, 1, 0, 7), // AIDR
REG_VFP32(KVM_REG_ARM_VFP_MVFR0),
REG_VFP32(KVM_REG_ARM_VFP_MVFR1),
REG_VFP32(KVM_REG_ARM_VFP_FPSID),
regVfp32(KVM_REG_ARM_VFP_MVFR0),
regVfp32(KVM_REG_ARM_VFP_MVFR1),
regVfp32(KVM_REG_ARM_VFP_FPSID),
REG_DEMUX32(KVM_REG_ARM_DEMUX_ID_CCSIDR, 0),
regDemux32(KVM_REG_ARM_DEMUX_ID_CCSIDR, 0),
};
const static uint64_t KVM_REG64_TTBR0(REG_CP64(15, 0, 2));
const static uint64_t KVM_REG64_TTBR1(REG_CP64(15, 1, 2));
const static uint64_t KVM_REG64_TTBR0(regCp64(15, 0, 2));
const static uint64_t KVM_REG64_TTBR1(regCp64(15, 1, 2));
#define INTERRUPT_ID(type, vcpu, irq) ( \
((type) << KVM_ARM_IRQ_TYPE_SHIFT) | \
((vcpu) << KVM_ARM_IRQ_VCPU_SHIFT) | \
((irq) << KVM_ARM_IRQ_NUM_SHIFT))
#define INTERRUPT_VCPU_IRQ(vcpu) \
INTERRUPT_ID(KVM_ARM_IRQ_TYPE_CPU, vcpu, KVM_ARM_IRQ_CPU_IRQ)
#define INTERRUPT_VCPU_FIQ(vcpu) \
INTERRUPT_ID(KVM_ARM_IRQ_TYPE_CPU, vcpu, KVM_ARM_IRQ_CPU_FIQ)
#define COUNT_OF(l) (sizeof(l) / sizeof(*l))
const std::set<uint64_t> ArmKvmCPU::invariant_regs(
invariant_reg_vector,
invariant_reg_vector + COUNT_OF(invariant_reg_vector));
std::begin(invariant_reg_vector), std::end(invariant_reg_vector));
ArmKvmCPU::KvmIntRegInfo ArmKvmCPU::kvmIntRegs[] = {
{ REG_CORE32(usr_regs.ARM_r0), INTREG_R0, "R0" },
{ REG_CORE32(usr_regs.ARM_r1), INTREG_R1, "R1" },
{ REG_CORE32(usr_regs.ARM_r2), INTREG_R2, "R2" },
{ REG_CORE32(usr_regs.ARM_r3), INTREG_R3, "R3" },
{ REG_CORE32(usr_regs.ARM_r4), INTREG_R4, "R4" },
{ REG_CORE32(usr_regs.ARM_r5), INTREG_R5, "R5" },
{ REG_CORE32(usr_regs.ARM_r6), INTREG_R6, "R6" },
{ REG_CORE32(usr_regs.ARM_r7), INTREG_R7, "R7" },
{ REG_CORE32(usr_regs.ARM_r8), INTREG_R8, "R8" },
{ REG_CORE32(usr_regs.ARM_r9), INTREG_R9, "R9" },
{ REG_CORE32(usr_regs.ARM_r10), INTREG_R10, "R10" },
{ REG_CORE32(usr_regs.ARM_fp), INTREG_R11, "R11" },
{ REG_CORE32(usr_regs.ARM_ip), INTREG_R12, "R12" },
{ REG_CORE32(usr_regs.ARM_sp), INTREG_R13, "R13(USR)" },
{ REG_CORE32(usr_regs.ARM_lr), INTREG_R14, "R14(USR)" },
regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r0), INTREG_R0, "R0"),
regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r1), INTREG_R1, "R1"),
regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r2), INTREG_R2, "R2"),
regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r3), INTREG_R3, "R3"),
regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r4), INTREG_R4, "R4"),
regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r5), INTREG_R5, "R5"),
regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r6), INTREG_R6, "R6"),
regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r7), INTREG_R7, "R7"),
regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r8), INTREG_R8, "R8"),
regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r9), INTREG_R9, "R9"),
regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r10), INTREG_R10, "R10"),
regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_fp), INTREG_R11, "R11"),
regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_ip), INTREG_R12, "R12"),
regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_sp), INTREG_R13, "R13(USR)"),
regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_lr), INTREG_R14, "R14(USR)"),
{ REG_CORE32(svc_regs[0]), INTREG_SP_SVC, "R13(SVC)" },
{ REG_CORE32(svc_regs[1]), INTREG_LR_SVC, "R14(SVC)" },
regCore32(KVM_REG_ARM_CORE_REG(svc_regs[0]), INTREG_SP_SVC, "R13(SVC)"),
regCore32(KVM_REG_ARM_CORE_REG(svc_regs[1]), INTREG_LR_SVC, "R14(SVC)"),
{ REG_CORE32(abt_regs[0]), INTREG_SP_ABT, "R13(ABT)" },
{ REG_CORE32(abt_regs[1]), INTREG_LR_ABT, "R14(ABT)" },
regCore32(KVM_REG_ARM_CORE_REG(abt_regs[0]), INTREG_SP_ABT, "R13(ABT)"),
regCore32(KVM_REG_ARM_CORE_REG(abt_regs[1]), INTREG_LR_ABT, "R14(ABT)"),
{ REG_CORE32(und_regs[0]), INTREG_SP_UND, "R13(UND)" },
{ REG_CORE32(und_regs[1]), INTREG_LR_UND, "R14(UND)" },
regCore32(KVM_REG_ARM_CORE_REG(und_regs[0]), INTREG_SP_UND, "R13(UND)"),
regCore32(KVM_REG_ARM_CORE_REG(und_regs[1]), INTREG_LR_UND, "R14(UND)"),
{ REG_CORE32(irq_regs[0]), INTREG_SP_IRQ, "R13(IRQ)" },
{ REG_CORE32(irq_regs[1]), INTREG_LR_IRQ, "R14(IRQ)" },
regCore32(KVM_REG_ARM_CORE_REG(irq_regs[0]), INTREG_SP_IRQ, "R13(IRQ)"),
regCore32(KVM_REG_ARM_CORE_REG(irq_regs[1]), INTREG_LR_IRQ, "R14(IRQ)"),
{ REG_CORE32(fiq_regs[0]), INTREG_R8_FIQ, "R8(FIQ)" },
{ REG_CORE32(fiq_regs[1]), INTREG_R9_FIQ, "R9(FIQ)" },
{ REG_CORE32(fiq_regs[2]), INTREG_R10_FIQ, "R10(FIQ)" },
{ REG_CORE32(fiq_regs[3]), INTREG_R11_FIQ, "R11(FIQ)" },
{ REG_CORE32(fiq_regs[4]), INTREG_R12_FIQ, "R12(FIQ)" },
{ REG_CORE32(fiq_regs[5]), INTREG_R13_FIQ, "R13(FIQ)" },
{ REG_CORE32(fiq_regs[6]), INTREG_R14_FIQ, "R14(FIQ)" },
regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[0]), INTREG_R8_FIQ, "R8(FIQ)"),
regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[1]), INTREG_R9_FIQ, "R9(FIQ)"),
regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[2]), INTREG_R10_FIQ, "R10(FIQ)"),
regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[3]), INTREG_R11_FIQ, "R11(FIQ)"),
regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[4]), INTREG_R12_FIQ, "R12(FIQ)"),
regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[5]), INTREG_R13_FIQ, "R13(FIQ)"),
regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[6]), INTREG_R14_FIQ, "R14(FIQ)"),
{ 0, NUM_INTREGS, NULL }
};
ArmKvmCPU::KvmCoreMiscRegInfo ArmKvmCPU::kvmCoreMiscRegs[] = {
{ REG_CORE32(usr_regs.ARM_cpsr), MISCREG_CPSR, "CPSR" },
{ REG_CORE32(svc_regs[2]), MISCREG_SPSR_SVC, "SPSR(SVC)" },
{ REG_CORE32(abt_regs[2]), MISCREG_SPSR_ABT, "SPSR(ABT)" },
{ REG_CORE32(und_regs[2]), MISCREG_SPSR_UND, "SPSR(UND)" },
{ REG_CORE32(irq_regs[2]), MISCREG_SPSR_IRQ, "SPSR(IRQ)" },
{ REG_CORE32(fiq_regs[2]), MISCREG_SPSR_FIQ, "SPSR(FIQ)" },
regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr), MISCREG_CPSR, "CPSR"),
regCore32(KVM_REG_ARM_CORE_REG(svc_regs[2]), MISCREG_SPSR_SVC,
"SPSR(SVC)"),
regCore32(KVM_REG_ARM_CORE_REG(abt_regs[2]), MISCREG_SPSR_ABT,
"SPSR(ABT)"),
regCore32(KVM_REG_ARM_CORE_REG(und_regs[2]), MISCREG_SPSR_UND,
"SPSR(UND)"),
regCore32(KVM_REG_ARM_CORE_REG(irq_regs[2]), MISCREG_SPSR_IRQ,
"SPSR(IRQ)"),
regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[2]), MISCREG_SPSR_FIQ,
"SPSR(FIQ)"),
{ 0, NUM_MISCREGS }
};
@@ -273,18 +365,18 @@ Tick
ArmKvmCPU::kvmRun(Tick ticks)
{
auto interrupt = static_cast<ArmISA::Interrupts *>(interrupts[0]);
const bool simFIQ(interrupt->checkRaw(INT_FIQ));
const bool simIRQ(interrupt->checkRaw(INT_IRQ));
const bool simFIQ = interrupt->checkRaw(INT_FIQ);
const bool simIRQ = interrupt->checkRaw(INT_IRQ);
if (fiqAsserted != simFIQ) {
fiqAsserted = simFIQ;
DPRINTF(KvmInt, "KVM: Update FIQ state: %i\n", simFIQ);
vm.setIRQLine(INTERRUPT_VCPU_FIQ(vcpuID), simFIQ);
vm.setIRQLine(interruptVcpuFiq(vcpuID), simFIQ);
}
if (irqAsserted != simIRQ) {
irqAsserted = simIRQ;
DPRINTF(KvmInt, "KVM: Update IRQ state: %i\n", simIRQ);
vm.setIRQLine(INTERRUPT_VCPU_IRQ(vcpuID), simIRQ);
vm.setIRQLine(interruptVcpuIrq(vcpuID), simIRQ);
}
return BaseKvmCPU::kvmRun(ticks);
@@ -320,7 +412,7 @@ ArmKvmCPU::getRegList() const
{
if (_regIndexList.size() == 0) {
std::unique_ptr<struct kvm_reg_list> regs;
uint64_t i(1);
uint64_t i = 1;
do {
i <<= 1;
@@ -358,18 +450,18 @@ ArmKvmCPU::kvmArmVCpuInit(const struct kvm_vcpu_init &init)
MiscRegIndex
ArmKvmCPU::decodeCoProcReg(uint64_t id) const
{
const unsigned cp(REG_CP(id));
const bool is_reg32(REG_IS_32BIT(id));
const bool is_reg64(REG_IS_64BIT(id));
const unsigned cp = regCp(id);
const bool is_reg32 = regIs32Bit(id);
const bool is_reg64 = regIs64Bit(id);
// CP numbers larger than 15 are reserved for KVM extensions
if (cp > 15)
return NUM_MISCREGS;
const unsigned crm(REG_CRM(id));
const unsigned crn(REG_CRN(id));
const unsigned opc1(REG_OPC1(id));
const unsigned opc2(REG_OPC2(id));
const unsigned crm = regCrm(id);
const unsigned crn = regCrn(id);
const unsigned opc1 = regOpc1(id);
const unsigned opc2 = regOpc2(id);
if (is_reg32) {
switch (cp) {
@@ -393,10 +485,10 @@ ArmKvmCPU::decodeCoProcReg(uint64_t id) const
ArmISA::MiscRegIndex
ArmKvmCPU::decodeVFPCtrlReg(uint64_t id) const
{
if (!REG_IS_ARM(id) || !REG_IS_VFP(id) || !REG_IS_VFP_CTRL(id))
if (!regIsArm(id) || !regIsVfp(id) || !regIsVfpCtrl(id))
return NUM_MISCREGS;
const unsigned vfp_reg(REG_VFP_REG(id));
const unsigned vfp_reg = regVfpReg(id);
switch (vfp_reg) {
case KVM_REG_ARM_VFP_FPSID: return MISCREG_FPSID;
case KVM_REG_ARM_VFP_FPSCR: return MISCREG_FPSCR;
@@ -420,7 +512,7 @@ ArmKvmCPU::isInvariantReg(uint64_t id)
/* Mask away the value field from multiplexed registers, we assume
* that entire groups of multiplexed registers can be treated as
* invariant. */
if (REG_IS_ARM(id) && REG_IS_DEMUX(id))
if (regIsArm(id) && regIsDemux(id))
id &= ~KVM_REG_ARM_DEMUX_VAL_MASK;
return invariant_regs.find(id) != invariant_regs.end();
@@ -445,7 +537,7 @@ void
ArmKvmCPU::dumpKvmStateCore()
{
/* Print core registers */
uint32_t pc(getOneRegU32(REG_CORE32(usr_regs.ARM_pc)));
uint32_t pc = getOneRegU32(REG_CORE32(usr_regs.ARM_pc));
inform("PC: 0x%x\n", pc);
for (const KvmIntRegInfo *ri(kvmIntRegs);
@@ -467,36 +559,33 @@ void
ArmKvmCPU::dumpKvmStateMisc()
{
/* Print co-processor registers */
const RegIndexVector &reg_ids(getRegList());;
const RegIndexVector &reg_ids = getRegList();
for (RegIndexVector::const_iterator it(reg_ids.begin());
it != reg_ids.end(); ++it) {
uint64_t id(*it);
uint64_t id = *it;
if (REG_IS_ARM(id) && REG_CP(id) <= 15) {
if (regIsArm(id) && regCp(id) <= 15) {
dumpKvmStateCoProc(id);
} else if (REG_IS_ARM(id) && REG_IS_VFP(id)) {
} else if (regIsArm(id) && regIsVfp(id)) {
dumpKvmStateVFP(id);
} else if (REG_IS_ARM(id) && REG_IS_DEMUX(id)) {
} else if (regIsArm(id) && regIsDemux(id)) {
switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
case KVM_REG_ARM_DEMUX_ID_CCSIDR:
inform("CCSIDR [0x%x]: %s\n",
EXTRACT_FIELD(id,
KVM_REG_ARM_DEMUX_VAL_MASK,
KVM_REG_ARM_DEMUX_VAL_SHIFT),
extractField(id, KVM_REG_ARM_DEMUX_VAL_MASK,
KVM_REG_ARM_DEMUX_VAL_SHIFT),
getAndFormatOneReg(id));
break;
default:
inform("DEMUX [0x%x, 0x%x]: %s\n",
EXTRACT_FIELD(id,
KVM_REG_ARM_DEMUX_ID_MASK,
KVM_REG_ARM_DEMUX_ID_SHIFT),
EXTRACT_FIELD(id,
KVM_REG_ARM_DEMUX_VAL_MASK,
KVM_REG_ARM_DEMUX_VAL_SHIFT),
extractField(id, KVM_REG_ARM_DEMUX_ID_MASK,
KVM_REG_ARM_DEMUX_ID_SHIFT),
extractField(id, KVM_REG_ARM_DEMUX_VAL_MASK,
KVM_REG_ARM_DEMUX_VAL_SHIFT),
getAndFormatOneReg(id));
break;
}
} else if (!REG_IS_CORE(id)) {
} else if (!regIsCore(id)) {
inform("0x%x: %s\n", id, getAndFormatOneReg(id));
}
}
@@ -505,41 +594,41 @@ ArmKvmCPU::dumpKvmStateMisc()
void
ArmKvmCPU::dumpKvmStateCoProc(uint64_t id)
{
assert(REG_IS_ARM(id));
assert(REG_CP(id) <= 15);
assert(regIsArm(id));
assert(regCp(id) <= 15);
if (REG_IS_32BIT(id)) {
if (regIs32Bit(id)) {
// 32-bit co-proc registers
MiscRegIndex idx(decodeCoProcReg(id));
uint32_t value(getOneRegU32(id));
MiscRegIndex idx = decodeCoProcReg(id);
uint32_t value = getOneRegU32(id);
if (idx != NUM_MISCREGS &&
!(idx >= MISCREG_CP15_UNIMP_START && idx < MISCREG_CP15_END)) {
const char *name(miscRegName[idx]);
const unsigned m5_ne(tc->readMiscRegNoEffect(idx));
const unsigned m5_e(tc->readMiscReg(idx));
const char *name = miscRegName[idx];
const unsigned m5_ne = tc->readMiscRegNoEffect(idx);
const unsigned m5_e = tc->readMiscReg(idx);
inform("CP%i: [CRn: c%i opc1: %.2i CRm: c%i opc2: %i inv: %i]: "
"[%s]: 0x%x/0x%x\n",
REG_CP(id), REG_CRN(id), REG_OPC1(id), REG_CRM(id),
REG_OPC2(id), isInvariantReg(id),
regCp(id), regCrn(id), regOpc1(id), regCrm(id),
regOpc2(id), isInvariantReg(id),
name, value, m5_e);
if (m5_e != m5_ne) {
inform("readMiscReg: %x, readMiscRegNoEffect: %x\n",
m5_e, m5_ne);
}
} else {
const char *name(idx != NUM_MISCREGS ? miscRegName[idx] : "-");
inform("CP%i: [CRn: c%i opc1: %.2i CRm: c%i opc2: %i inv: %i]: [%s]: "
"0x%x\n",
REG_CP(id), REG_CRN(id), REG_OPC1(id), REG_CRM(id),
REG_OPC2(id), isInvariantReg(id), name, value);
const char *name = idx != NUM_MISCREGS ? miscRegName[idx] : "-";
inform("CP%i: [CRn: c%i opc1: %.2i CRm: c%i opc2: %i inv: %i]: "
"[%s]: 0x%x\n",
regCp(id), regCrn(id), regOpc1(id), regCrm(id),
regOpc2(id), isInvariantReg(id), name, value);
}
} else {
inform("CP%i: [CRn: c%i opc1: %.2i CRm: c%i opc2: %i inv: %i "
"len: 0x%x]: %s\n",
REG_CP(id), REG_CRN(id), REG_OPC1(id), REG_CRM(id),
REG_OPC2(id), isInvariantReg(id),
EXTRACT_FIELD(id, KVM_REG_SIZE_MASK, KVM_REG_SIZE_SHIFT),
regCp(id), regCrn(id), regOpc1(id), regCrm(id),
regOpc2(id), isInvariantReg(id),
extractField(id, KVM_REG_SIZE_MASK, KVM_REG_SIZE_SHIFT),
getAndFormatOneReg(id));
}
}
@@ -547,14 +636,14 @@ ArmKvmCPU::dumpKvmStateCoProc(uint64_t id)
void
ArmKvmCPU::dumpKvmStateVFP(uint64_t id)
{
assert(REG_IS_ARM(id));
assert(REG_IS_VFP(id));
assert(regIsArm(id));
assert(regIsVfp(id));
if (REG_IS_VFP_REG(id)) {
const unsigned idx(id & KVM_REG_ARM_VFP_MASK);
if (regIsVfpReg(id)) {
const unsigned idx = id & KVM_REG_ARM_VFP_MASK;
inform("VFP reg %i: %s", idx, getAndFormatOneReg(id));
} else if (REG_IS_VFP_CTRL(id)) {
MiscRegIndex idx(decodeVFPCtrlReg(id));
} else if (regIsVfpCtrl(id)) {
MiscRegIndex idx = decodeVFPCtrlReg(id);
if (idx != NUM_MISCREGS) {
inform("VFP [%s]: %s", miscRegName[idx], getAndFormatOneReg(id));
} else {
@@ -571,7 +660,7 @@ ArmKvmCPU::updateKvmStateCore()
for (const KvmIntRegInfo *ri(kvmIntRegs);
ri->idx != NUM_INTREGS; ++ri) {
uint64_t value(tc->readIntRegFlat(ri->idx));
uint64_t value = tc->readIntRegFlat(ri->idx);
DPRINTF(KvmContext, "kvm(%s) := 0x%x\n", ri->name, value);
setOneReg(ri->id, value);
}
@@ -582,7 +671,7 @@ ArmKvmCPU::updateKvmStateCore()
for (const KvmCoreMiscRegInfo *ri(kvmCoreMiscRegs);
ri->idx != NUM_MISCREGS; ++ri) {
uint64_t value(tc->readMiscReg(ri->idx));
uint64_t value = tc->readMiscReg(ri->idx);
DPRINTF(KvmContext, "kvm(%s) := 0x%x\n", ri->name, value);
setOneReg(ri->id, value);
}
@@ -594,31 +683,31 @@ ArmKvmCPU::updateKvmStateCore()
void
ArmKvmCPU::updateKvmStateMisc()
{
static bool warned(false); // We can't use warn_once since we want
// to show /all/ registers
static bool warned = false; // We can't use warn_once since we want
// to show /all/ registers
const RegIndexVector &regs(getRegList());
const RegIndexVector &regs = getRegList();
for (RegIndexVector::const_iterator it(regs.begin());
it != regs.end();
++it) {
if (!REG_IS_ARM(*it)) {
if (!regIsArm(*it)) {
if (!warned)
warn("Skipping non-ARM register: 0x%x\n", *it);
} else if (isInvariantReg(*it)) {
DPRINTF(Kvm, "Skipping invariant register: 0x%x\n", *it);
} else if (REG_IS_CORE(*it)) {
} else if (regIsCore(*it)) {
// Core registers are handled in updateKvmStateCore
continue;
} else if (REG_CP(*it) <= 15) {
} else if (regCp(*it) <= 15) {
updateKvmStateCoProc(*it, !warned);
} else if (REG_IS_VFP(*it)) {
} else if (regIsVfp(*it)) {
updateKvmStateVFP(*it, !warned);
} else {
if (!warned) {
warn("Skipping register with unknown CP (%i) id: 0x%x\n",
REG_CP(*it), *it);
regCp(*it), *it);
}
}
@@ -632,10 +721,10 @@ ArmKvmCPU::updateKvmStateMisc()
void
ArmKvmCPU::updateKvmStateCoProc(uint64_t id, bool show_warnings)
{
MiscRegIndex reg(decodeCoProcReg(id));
MiscRegIndex reg = decodeCoProcReg(id);
assert(REG_IS_ARM(id));
assert(REG_CP(id) <= 15);
assert(regIsArm(id));
assert(regCp(id) <= 15);
if (id == KVM_REG64_TTBR0 || id == KVM_REG64_TTBR1) {
// HACK HACK HACK: Workaround for 64-bit TTBRx
@@ -650,8 +739,8 @@ ArmKvmCPU::updateKvmStateCoProc(uint64_t id, bool show_warnings)
id);
warn("\t0x%x: [CP: %i 64: %i CRn: c%i opc1: %.2i CRm: c%i"
" opc2: %i]\n",
id, REG_CP(id), REG_IS_64BIT(id), REG_CRN(id),
REG_OPC1(id), REG_CRM(id), REG_OPC2(id));
id, regCp(id), regIs64Bit(id), regCrn(id),
regOpc1(id), regCrm(id), regOpc2(id));
}
} else if (reg >= MISCREG_CP15_UNIMP_START && reg < MISCREG_CP15_END) {
if (show_warnings)
@@ -666,32 +755,32 @@ ArmKvmCPU::updateKvmStateCoProc(uint64_t id, bool show_warnings)
void
ArmKvmCPU::updateKvmStateVFP(uint64_t id, bool show_warnings)
{
assert(REG_IS_ARM(id));
assert(REG_IS_VFP(id));
assert(regIsArm(id));
assert(regIsVfp(id));
if (REG_IS_VFP_REG(id)) {
if (!REG_IS_64BIT(id)) {
if (regIsVfpReg(id)) {
if (!regIs64Bit(id)) {
if (show_warnings)
warn("Unexpected VFP register length (reg: 0x%x).\n", id);
return;
}
const unsigned idx(id & KVM_REG_ARM_VFP_MASK);
const unsigned idx_base(idx << 1);
const unsigned idx_hi(idx_base + 1);
const unsigned idx_lo(idx_base + 0);
uint64_t value(
const unsigned idx = id & KVM_REG_ARM_VFP_MASK;
const unsigned idx_base = idx << 1;
const unsigned idx_hi = idx_base + 1;
const unsigned idx_lo = idx_base + 0;
uint64_t value =
((uint64_t)tc->readFloatRegFlat(idx_hi) << 32) |
tc->readFloatRegFlat(idx_lo));
tc->readFloatRegFlat(idx_lo);
setOneReg(id, value);
} else if (REG_IS_VFP_CTRL(id)) {
MiscRegIndex idx(decodeVFPCtrlReg(id));
} else if (regIsVfpCtrl(id)) {
MiscRegIndex idx = decodeVFPCtrlReg(id);
if (idx == NUM_MISCREGS) {
if (show_warnings)
warn("Unhandled VFP control register: 0x%x\n", id);
return;
}
if (!REG_IS_32BIT(id)) {
if (!regIs32Bit(id)) {
if (show_warnings)
warn("Ignoring VFP control register (%s) with "
"unexpected size.\n",
@@ -727,7 +816,7 @@ ArmKvmCPU::updateTCStateCore()
// We update the PC state after we have updated the CPSR the
// contents of the CPSR affects how the npc is updated.
PCState pc(tc->pcState());
PCState pc = tc->pcState();
pc.set(getOneRegU32(REG_CORE32(usr_regs.ARM_pc)));
tc->pcState(pc);
@@ -741,23 +830,23 @@ ArmKvmCPU::updateTCStateMisc()
static bool warned(false); // We can't use warn_once since we want
// to show /all/ registers
const RegIndexVector &reg_ids(getRegList());;
const RegIndexVector &reg_ids = getRegList();
for (RegIndexVector::const_iterator it(reg_ids.begin());
it != reg_ids.end(); ++it) {
if (!REG_IS_ARM(*it)) {
if (!regIsArm(*it)) {
if (!warned)
warn("Skipping non-ARM register: 0x%x\n", *it);
} else if (REG_IS_CORE(*it)) {
} else if (regIsCore(*it)) {
// Core registers are handled in updateKvmStateCore
} else if (REG_CP(*it) <= 15) {
} else if (regCp(*it) <= 15) {
updateTCStateCoProc(*it, !warned);
} else if (REG_IS_VFP(*it)) {
} else if (regIsVfp(*it)) {
updateTCStateVFP(*it, !warned);
} else {
if (!warned) {
warn("Skipping register with unknown CP (%i) id: 0x%x\n",
REG_CP(*it), *it);
regCp(*it), *it);
}
}
}
@@ -771,10 +860,10 @@ ArmKvmCPU::updateTCStateMisc()
void
ArmKvmCPU::updateTCStateCoProc(uint64_t id, bool show_warnings)
{
MiscRegIndex reg(decodeCoProcReg(id));
MiscRegIndex reg = decodeCoProcReg(id);
assert(REG_IS_ARM(id));
assert(REG_CP(id) <= 15);
assert(regIsArm(id));
assert(regCp(id) <= 15);
if (id == KVM_REG64_TTBR0 || id == KVM_REG64_TTBR1) {
// HACK HACK HACK: We don't currently support 64-bit TTBR0/TTBR1
@@ -783,7 +872,7 @@ ArmKvmCPU::updateTCStateCoProc(uint64_t id, bool show_warnings)
id == KVM_REG64_TTBR0 ? MISCREG_TTBR0 : MISCREG_TTBR1,
(uint32_t)(getOneRegU64(id) & 0xFFFFFFFF));
} else if (reg == MISCREG_TTBCR) {
uint32_t value(getOneRegU64(id));
uint32_t value = getOneRegU64(id);
if (value & 0x80000000)
panic("KVM: Guest tried to enable LPAE.\n");
tc->setMiscRegNoEffect(reg, value);
@@ -792,8 +881,8 @@ ArmKvmCPU::updateTCStateCoProc(uint64_t id, bool show_warnings)
warn("KVM: Ignoring unknown KVM co-processor register:\n", id);
warn("\t0x%x: [CP: %i 64: %i CRn: c%i opc1: %.2i CRm: c%i"
" opc2: %i]\n",
id, REG_CP(id), REG_IS_64BIT(id), REG_CRN(id),
REG_OPC1(id), REG_CRM(id), REG_OPC2(id));
id, regCp(id), regIs64Bit(id), regCrn(id),
regOpc1(id), regCrm(id), regOpc2(id));
}
} else if (reg >= MISCREG_CP15_UNIMP_START && reg < MISCREG_CP15_END) {
if (show_warnings)
@@ -807,31 +896,31 @@ ArmKvmCPU::updateTCStateCoProc(uint64_t id, bool show_warnings)
void
ArmKvmCPU::updateTCStateVFP(uint64_t id, bool show_warnings)
{
assert(REG_IS_ARM(id));
assert(REG_IS_VFP(id));
assert(regIsArm(id));
assert(regIsVfp(id));
if (REG_IS_VFP_REG(id)) {
if (!REG_IS_64BIT(id)) {
if (regIsVfpReg(id)) {
if (!regIs64Bit(id)) {
if (show_warnings)
warn("Unexpected VFP register length (reg: 0x%x).\n", id);
return;
}
const unsigned idx(id & KVM_REG_ARM_VFP_MASK);
const unsigned idx_base(idx << 1);
const unsigned idx_hi(idx_base + 1);
const unsigned idx_lo(idx_base + 0);
uint64_t value(getOneRegU64(id));
const unsigned idx = id & KVM_REG_ARM_VFP_MASK;
const unsigned idx_base = idx << 1;
const unsigned idx_hi = idx_base + 1;
const unsigned idx_lo = idx_base + 0;
uint64_t value = getOneRegU64(id);
tc->setFloatRegFlat(idx_hi, (value >> 32) & 0xFFFFFFFF);
tc->setFloatRegFlat(idx_lo, value & 0xFFFFFFFF);
} else if (REG_IS_VFP_CTRL(id)) {
MiscRegIndex idx(decodeVFPCtrlReg(id));
} else if (regIsVfpCtrl(id)) {
MiscRegIndex idx = decodeVFPCtrlReg(id);
if (idx == NUM_MISCREGS) {
if (show_warnings)
warn("Unhandled VFP control register: 0x%x\n", id);
return;
}
if (!REG_IS_32BIT(id)) {
if (!regIs32Bit(id)) {
if (show_warnings)
warn("Ignoring VFP control register (%s) with "
"unexpected size.\n",