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arch,cpu: "virtualize" the TLB interface.

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CPUs have historically instantiated the architecture specific version
of the TLBs to avoid a virtual function call, making them a little bit
more dependent on what the current ISA is. Some simple performance
measurement, the x86 twolf regression on the atomic CPU, shows that
there isn't actually any performance benefit, and if anything the
simulator goes slightly faster (although still within margin of error)
when the TLB functions are virtual.

This change switches everything outside of the architectures themselves
to use the generic BaseTLB type, and then inside the ISA for them to
cast that to their architecture specific type to call into architecture
specific interfaces.

The ARM TLB needed the most adjustment since it was using non-standard
translation function signatures. Specifically, they all took an extra
"type" parameter which defaulted to normal, and translateTiming
returned a Fault. translateTiming actually doesn't need to return a
Fault because everywhere that consumed it just stored it into a
structure which it then deleted(?), and the fault is stored in the
Translation object when the translation is done.

A little more work is needed to fully obviate the arch/tlb.hh header,
so the TheISA::TLB type is still visible outside of the ISAs.
Specifically, the TlbEntry type is used in the generic PageTable which
lives in src/mem.

Change-Id: I51b68ee74411f9af778317eff222f9349d2ed575
Reviewed-on: https://gem5-review.googlesource.com/6921
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
This commit is contained in:
Gabe Black
2017-12-22 01:07:55 -08:00
parent 4ac0a01e2f
commit b7618c69a5
42 changed files with 318 additions and 314 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/cpu/base.cc
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@@ -51,7 +51,7 @@
#include <sstream>
#include <string>
#include "arch/tlb.hh"
#include "arch/generic/tlb.hh"
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
#include "base/logging.hh"
@@ -313,7 +313,7 @@ BaseCPU::mwait(ThreadID tid, PacketPtr pkt)
}
void
BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, TheISA::TLB *dtb)
BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb)
{
assert(tid < numThreads);
AddressMonitor &monitor = addressMonitor[tid];

2
src/cpu/base.hh
View File

@@ -626,7 +626,7 @@ class BaseCPU : public MemObject
public:
void armMonitor(ThreadID tid, Addr address);
bool mwait(ThreadID tid, PacketPtr pkt);
void mwaitAtomic(ThreadID tid, ThreadContext *tc, TheISA::TLB *dtb);
void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb);
AddressMonitor *getCpuAddrMonitor(ThreadID tid)
{
assert(tid < numThreads);

15
src/cpu/checker/cpu.hh
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@@ -62,12 +62,7 @@
#include "params/CheckerCPU.hh"
#include "sim/eventq.hh"
// forward declarations
namespace TheISA
{
class TLB;
}
class BaseTLB;
template <class>
class BaseDynInst;
class ThreadContext;
@@ -140,8 +135,8 @@ class CheckerCPU : public BaseCPU, public ExecContext
ThreadContext *tc;
TheISA::TLB *itb;
TheISA::TLB *dtb;
BaseTLB *itb;
BaseTLB *dtb;
Addr dbg_vtophys(Addr addr);
@@ -166,8 +161,8 @@ class CheckerCPU : public BaseCPU, public ExecContext
// Primary thread being run.
SimpleThread *thread;
TheISA::TLB* getITBPtr() { return itb; }
TheISA::TLB* getDTBPtr() { return dtb; }
BaseTLB* getITBPtr() { return itb; }
BaseTLB* getDTBPtr() { return dtb; }
virtual Counter totalInsts() const override
{

4
src/cpu/checker/thread_context.hh
View File

@@ -112,9 +112,9 @@ class CheckerThreadContext : public ThreadContext
actualTC->setThreadId(id);
}
TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
BaseTLB *getITBPtr() { return actualTC->getITBPtr(); }
TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); }
CheckerCPU *getCheckerCpuPtr()
{

4
src/cpu/o3/cpu.hh
View File

@@ -123,8 +123,8 @@ class FullO3CPU : public BaseO3CPU
SwitchedOut
};
TheISA::TLB * itb;
TheISA::TLB * dtb;
BaseTLB *itb;
BaseTLB *dtb;
/** Overall CPU status. */
Status _status;

2
src/cpu/o3/fetch_impl.hh
View File

@@ -51,8 +51,8 @@
#include <map>
#include <queue>
#include "arch/generic/tlb.hh"
#include "arch/isa_traits.hh"
#include "arch/tlb.hh"
#include "arch/utility.hh"
#include "arch/vtophys.hh"
#include "base/random.hh"

4
src/cpu/o3/thread_context.hh
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@@ -79,10 +79,10 @@ class O3ThreadContext : public ThreadContext
O3ThreadState<Impl> *thread;
/** Returns a pointer to the ITB. */
TheISA::TLB *getITBPtr() { return cpu->itb; }
BaseTLB *getITBPtr() { return cpu->itb; }
/** Returns a pointer to the DTB. */
TheISA::TLB *getDTBPtr() { return cpu->dtb; }
BaseTLB *getDTBPtr() { return cpu->dtb; }
CheckerCPU *getCheckerCpuPtr() { return NULL; }

1
src/cpu/simple/base.cc
View File

@@ -45,7 +45,6 @@
#include "arch/kernel_stats.hh"
#include "arch/stacktrace.hh"
#include "arch/tlb.hh"
#include "arch/utility.hh"
#include "arch/vtophys.hh"
#include "base/cp_annotate.hh"

6
src/cpu/simple_thread.cc
View File

@@ -62,8 +62,8 @@ using namespace std;
// constructor
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
Process *_process, TheISA::TLB *_itb,
TheISA::TLB *_dtb, TheISA::ISA *_isa)
Process *_process, BaseTLB *_itb,
BaseTLB *_dtb, TheISA::ISA *_isa)
: ThreadState(_cpu, _thread_num, _process), isa(_isa),
predicate(false), system(_sys),
itb(_itb), dtb(_dtb)
@@ -74,7 +74,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
}
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
TheISA::TLB *_itb, TheISA::TLB *_dtb,
BaseTLB *_itb, BaseTLB *_dtb,
TheISA::ISA *_isa, bool use_kernel_stats)
: ThreadState(_cpu, _thread_num, NULL), isa(_isa), system(_sys), itb(_itb),
dtb(_dtb)

14
src/cpu/simple_thread.hh
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@@ -46,10 +46,10 @@
#define __CPU_SIMPLE_THREAD_HH__
#include "arch/decoder.hh"
#include "arch/generic/tlb.hh"
#include "arch/isa.hh"
#include "arch/isa_traits.hh"
#include "arch/registers.hh"
#include "arch/tlb.hh"
#include "arch/types.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
@@ -135,19 +135,19 @@ class SimpleThread : public ThreadState
System *system;
TheISA::TLB *itb;
TheISA::TLB *dtb;
BaseTLB *itb;
BaseTLB *dtb;
TheISA::Decoder decoder;
// constructor: initialize SimpleThread from given process structure
// FS
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa,
BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa,
bool use_kernel_stats = true);
// SE
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb,
Process *_process, BaseTLB *_itb, BaseTLB *_dtb,
TheISA::ISA *_isa);
virtual ~SimpleThread();
@@ -201,9 +201,9 @@ class SimpleThread : public ThreadState
BaseCPU *getCpuPtr() { return baseCpu; }
TheISA::TLB *getITBPtr() { return itb; }
BaseTLB *getITBPtr() { return itb; }
TheISA::TLB *getDTBPtr() { return dtb; }
BaseTLB *getDTBPtr() { return dtb; }
CheckerCPU *getCheckerCpuPtr() { return NULL; }

10
src/cpu/thread_context.hh
View File

@@ -58,9 +58,9 @@
namespace TheISA
{
class Decoder;
class TLB;
}
class BaseCPU;
class BaseTLB;
class CheckerCPU;
class Checkpoint;
class EndQuiesceEvent;
@@ -136,9 +136,9 @@ class ThreadContext
virtual void setContextId(int id) = 0;
virtual TheISA::TLB *getITBPtr() = 0;
virtual BaseTLB *getITBPtr() = 0;
virtual TheISA::TLB *getDTBPtr() = 0;
virtual BaseTLB *getDTBPtr() = 0;
virtual CheckerCPU *getCheckerCpuPtr() = 0;
@@ -394,9 +394,9 @@ class ProxyThreadContext : public ThreadContext
void setContextId(int id) { actualTC->setContextId(id); }
TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
BaseTLB *getITBPtr() { return actualTC->getITBPtr(); }
TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); }
CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }