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cpu,misc: Revert problematic terminology renames in BaseCPU

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Due to gem5's use of duck-typing, we must termorarly revert the
terminology in BaseCPU back to master/slave to avoid issues.

This fixes https://gem5.atlassian.net/browse/GEM5-775.

Change-Id: Idf1cb99aa9568ee70943ebec96f27394d8167f8c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34495
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Bobby R. Bruce
2020-09-14 20:29:24 -07:00
parent 90a6e80962
commit b5850b69d1
1 changed files with 3 additions and 3 deletions
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6
src/cpu/BaseCPU.py
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@@ -194,13 +194,13 @@ class BaseCPU(ClockedObject):
def connectCachedPorts(self, bus):
for p in self._cached_ports:
exec('self.%s = bus.cpu_side_ports' % p)
exec('self.%s = bus.slave' % p)
def connectUncachedPorts(self, bus):
for p in self._uncached_interrupt_response_ports:
exec('self.%s = bus.mem_side_ports' % p)
exec('self.%s = bus.master' % p)
for p in self._uncached_interrupt_request_ports:
exec('self.%s = bus.cpu_side_ports' % p)
exec('self.%s = bus.slave' % p)
def connectAllPorts(self, cached_bus, uncached_bus = None):
self.connectCachedPorts(cached_bus)