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dev: Rename iGbReg namespace as igbreg

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As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::iGbReg became ::igbreg.

Change-Id: I4b19503c8cda37248667464be0ac4fd9a7bb42d8
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45391
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Daniel R. Carvalho
2021-05-08 09:01:03 -03:00
committed by Daniel Carvalho
parent debb13905b
commit b571b17626
3 changed files with 18 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/dev/net/i8254xGBe.cc
View File

@@ -52,7 +52,7 @@
#include "sim/stats.hh"
#include "sim/system.hh"
using namespace iGbReg;
using namespace igbreg;
using namespace Net;
IGbE::IGbE(const Params &p)
@@ -1898,7 +1898,7 @@ IGbE::TxDescCache::actionAfterWb()
{
DPRINTF(EthernetDesc, "actionAfterWb() completionEnabled: %d\n",
completionEnabled);
igbe->postInterrupt(iGbReg::IT_TXDW);
igbe->postInterrupt(igbreg::IT_TXDW);
if (completionEnabled) {
descEnd = igbe->regs.tdh();
DPRINTF(EthernetDesc,
@@ -2365,7 +2365,7 @@ IGbE::serialize(CheckpointOut &cp) const
SERIALIZE_SCALAR(eeOpcode);
SERIALIZE_SCALAR(eeAddr);
SERIALIZE_SCALAR(lastInterrupt);
SERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE);
SERIALIZE_ARRAY(flash,igbreg::EEPROM_SIZE);
rxFifo.serialize("rxfifo", cp);
txFifo.serialize("txfifo", cp);
@@ -2416,7 +2416,7 @@ IGbE::unserialize(CheckpointIn &cp)
UNSERIALIZE_SCALAR(eeOpcode);
UNSERIALIZE_SCALAR(eeAddr);
UNSERIALIZE_SCALAR(lastInterrupt);
UNSERIALIZE_ARRAY(flash,iGbReg::EEPROM_SIZE);
UNSERIALIZE_ARRAY(flash,igbreg::EEPROM_SIZE);
rxFifo.unserialize("rxfifo", cp);
txFifo.unserialize("txfifo", cp);

20
src/dev/net/i8254xGBe.hh
View File

@@ -60,12 +60,12 @@ class IGbE : public EtherDevice
IGbEInt *etherInt;
// device registers
iGbReg::Regs regs;
igbreg::Regs regs;
// eeprom data, status and control bits
int eeOpBits, eeAddrBits, eeDataBits;
uint8_t eeOpcode, eeAddr;
uint16_t flash[iGbReg::EEPROM_SIZE];
uint16_t flash[igbreg::EEPROM_SIZE];
// packet fifos
PacketFifo rxFifo;
@@ -95,7 +95,7 @@ class IGbE : public EtherDevice
rxDescCache.writeback(0);
DPRINTF(EthernetIntr,
"Posting RXT interrupt because RDTR timer expired\n");
postInterrupt(iGbReg::IT_RXT);
postInterrupt(igbreg::IT_RXT);
}
EventFunctionWrapper rdtrEvent;
@@ -105,7 +105,7 @@ class IGbE : public EtherDevice
rxDescCache.writeback(0);
DPRINTF(EthernetIntr,
"Posting RXT interrupt because RADV timer expired\n");
postInterrupt(iGbReg::IT_RXT);
postInterrupt(igbreg::IT_RXT);
}
EventFunctionWrapper radvEvent;
@@ -115,7 +115,7 @@ class IGbE : public EtherDevice
txDescCache.writeback(0);
DPRINTF(EthernetIntr,
"Posting TXDW interrupt because TADV timer expired\n");
postInterrupt(iGbReg::IT_TXDW);
postInterrupt(igbreg::IT_TXDW);
}
EventFunctionWrapper tadvEvent;
@@ -125,7 +125,7 @@ class IGbE : public EtherDevice
txDescCache.writeback(0);
DPRINTF(EthernetIntr,
"Posting TXDW interrupt because TIDV timer expired\n");
postInterrupt(iGbReg::IT_TXDW);
postInterrupt(igbreg::IT_TXDW);
}
EventFunctionWrapper tidvEvent;
@@ -145,7 +145,7 @@ class IGbE : public EtherDevice
* @param t the type of interrupt we are posting
* @param now should we ignore the interrupt limiting timer
*/
void postInterrupt(iGbReg::IntTypes t, bool now = false);
void postInterrupt(igbreg::IntTypes t, bool now = false);
/** Check and see if changes to the mask register have caused an interrupt
* to need to be sent or perhaps removed an interrupt cause.
@@ -299,7 +299,7 @@ class IGbE : public EtherDevice
};
class RxDescCache : public DescCache<iGbReg::RxDesc>
class RxDescCache : public DescCache<igbreg::RxDesc>
{
protected:
Addr descBase() const override { return igbe->regs.rdba(); }
@@ -360,7 +360,7 @@ class IGbE : public EtherDevice
RxDescCache rxDescCache;
class TxDescCache : public DescCache<iGbReg::TxDesc>
class TxDescCache : public DescCache<igbreg::TxDesc>
{
protected:
Addr descBase() const override { return igbe->regs.tdba(); }
@@ -418,7 +418,7 @@ class IGbE : public EtherDevice
unsigned
descInBlock(unsigned num_desc)
{
return num_desc / igbe->cacheBlockSize() / sizeof(iGbReg::TxDesc);
return num_desc / igbe->cacheBlockSize() / sizeof(igbreg::TxDesc);
}
/** Ask if the packet has been transfered so the state machine can give

7
src/dev/net/i8254xGBe_defs.hh
View File

@@ -32,8 +32,9 @@
#include "base/bitfield.hh"
#include "base/compiler.hh"
namespace iGbReg {
GEM5_DEPRECATED_NAMESPACE(iGbReg, igbreg);
namespace igbreg
{
// Registers used by the Intel GbE NIC
const uint32_t REG_CTRL = 0x00000;
@@ -939,4 +940,4 @@ struct Regs : public Serializable
UNSERIALIZE_SCALAR(sw_fw_sync);
}
};
} // namespace iGbReg
} // namespace igbreg