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arm: Use MiscRegIndex rather than int when flattening

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Some additional type checking to avoid future issues.
This commit is contained in:
Andreas Hansson
2014-10-01 08:05:52 -04:00
parent 10f82934be
commit b520223699
3 changed files with 14 additions and 11 deletions
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14
src/arch/arm/miscregs.cc
View File

@@ -2034,22 +2034,24 @@ canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
}
int
flattenMiscRegNsBanked(int reg, ThreadContext *tc)
flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc)
{
int reg_as_int = static_cast<int>(reg);
if (miscRegInfo[reg][MISCREG_BANKED]) {
SCR scr = tc->readMiscReg(MISCREG_SCR);
reg += (ArmSystem::haveSecurity(tc) && !scr.ns) ? 2 : 1;
reg_as_int += (ArmSystem::haveSecurity(tc) && !scr.ns) ? 2 : 1;
}
return reg;
return reg_as_int;
}
int
flattenMiscRegNsBanked(int reg, ThreadContext *tc, bool ns)
flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns)
{
int reg_as_int = static_cast<int>(reg);
if (miscRegInfo[reg][MISCREG_BANKED]) {
reg += (ArmSystem::haveSecurity(tc) && !ns) ? 2 : 1;
reg_as_int += (ArmSystem::haveSecurity(tc) && !ns) ? 2 : 1;
}
return reg;
return reg_as_int;
}

4
src/arch/arm/miscregs.hh
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@@ -1859,14 +1859,14 @@ namespace ArmISA
// Uses just the scr.ns bit to pre flatten the misc regs. This is useful
// for MCR/MRC instructions
int
flattenMiscRegNsBanked(int reg, ThreadContext *tc);
flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc);
// Flattens a misc reg index using the specified security state. This is
// used for opperations (eg address translations) where the security
// state of the register access may differ from the current state of the
// processor
int
flattenMiscRegNsBanked(int reg, ThreadContext *tc, bool ns);
flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns);
// Takes a misc reg index and returns the root reg if its one of a set of
// banked registers

7
src/arch/arm/table_walker.cc
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@@ -1158,9 +1158,10 @@ TableWalker::memAttrsLPAE(ThreadContext *tc, TlbEntry &te,
// LPAE always uses remapping of memory attributes, irrespective of the
// value of SCTLR.TRE
int reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0;
reg = flattenMiscRegNsBanked(reg, currState->tc, !currState->isSecure);
uint32_t mair = currState->tc->readMiscReg(reg);
MiscRegIndex reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0;
int reg_as_int = flattenMiscRegNsBanked(reg, currState->tc,
!currState->isSecure);
uint32_t mair = currState->tc->readMiscReg(reg_as_int);
attr = (mair >> (8 * (attrIndx % 4))) & 0xff;
uint8_t attr_7_4 = bits(attr, 7, 4);
uint8_t attr_3_0 = bits(attr, 3, 0);