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base,tests: Expanded GTests for addr_range.hh

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These tests assume the "end address" is not included in the range. This
exposed some bugs in addr_range.hh which have been fixed. Where
appropriate code comments in addr_range.hh have been extended to improve
understanding of the class's behavior.

Hard-coded AddrRange values in the project have been updated to take
into account that end address is now exclusive. The python params.py
interface has been updated to conform to this new standard.

Change-Id: Idd1e75d5771d198c4b8142b28de0f3a6e9007a52
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22427
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Brandon Potter
2019-10-18 14:43:14 -04:00
committed by Bobby R. Bruce
parent 1c4d64fb10
commit b4c9996d89
9 changed files with 1026 additions and 227 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/arch/x86/tlb.cc
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@@ -229,7 +229,7 @@ TLB::finalizePhysical(const RequestPtr &req,
{
Addr paddr = req->getPaddr();
AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF);
AddrRange m5opRange(0xFFFF0000, 0x100000000);
if (m5opRange.contains(paddr)) {
req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR |
@@ -241,7 +241,7 @@ TLB::finalizePhysical(const RequestPtr &req,
LocalApicBase localApicBase =
tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
AddrRange apicRange(localApicBase.base * PageBytes,
(localApicBase.base + 1) * PageBytes - 1);
(localApicBase.base + 1) * PageBytes);
if (apicRange.contains(paddr)) {
// The Intel developer's manuals say the below restrictions apply,

28
src/base/addr_range.hh
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@@ -75,7 +75,8 @@ class AddrRange
private:
/// Private fields for the start and end of the range
/// Both _start and _end are part of the range.
/// _start is the beginning of the range (inclusive).
/// _end is not part of the range.
Addr _start;
Addr _end;
@@ -121,7 +122,7 @@ class AddrRange
* @param _start The start address of this range
* @param _end The end address of this range (not included in the range)
* @param _masks The input vector of masks
* @param intlv_math The matching value of the xor operations
* @param intlv_match The matching value of the xor operations
*/
AddrRange(Addr _start, Addr _end, const std::vector<Addr> &_masks,
uint8_t _intlv_match)
@@ -155,7 +156,8 @@ class AddrRange
* @param _end The end address of this range (not included in the range)
* @param _intlv_high_bit The MSB of the intlv bits (disabled if 0)
* @param _xor_high_bit The MSB of the xor bit (disabled if 0)
* @param intlv_math The matching value of the xor operations
* @param _intlv_bits the size, in bits, of the intlv and xor bits
* @param intlv_match The matching value of the xor operations
*/
AddrRange(Addr _start, Addr _end, uint8_t _intlv_high_bit,
uint8_t _xor_high_bit, uint8_t _intlv_bits,
@@ -281,7 +283,7 @@ class AddrRange
*/
Addr size() const
{
return (_end - _start + 1) >> masks.size();
return (_end - _start) >> masks.size();
}
/**
@@ -348,7 +350,7 @@ class AddrRange
*/
bool intersects(const AddrRange& r) const
{
if (_start > r._end || _end < r._start)
if (_start >= r._end || _end <= r._start)
// start with the simple case of no overlap at all,
// applicable even if we have interleaved ranges
return false;
@@ -406,7 +408,7 @@ class AddrRange
// check if the address is in the range and if there is either
// no interleaving, or with interleaving also if the selected
// bits from the address match the interleaving value
bool in_range = a >= _start && a <= _end;
bool in_range = a >= _start && a < _end;
if (in_range) {
auto sel = 0;
for (int i = 0; i < masks.size(); i++) {
@@ -441,7 +443,7 @@ class AddrRange
* | 0 | a_high | a_mid | a_low |
* ---------------------------------
*
* @param the input address
* @param a the input address
* @return the new address
*/
inline Addr removeIntlvBits(Addr a) const
@@ -521,7 +523,7 @@ class AddrRange
*/
Addr getOffset(const Addr& a) const
{
bool in_range = a >= _start && a <= _end;
bool in_range = a >= _start && a < _end;
if (!in_range) {
return MaxAddr;
}
@@ -572,14 +574,14 @@ typedef std::list<AddrRange> AddrRangeList;
inline AddrRange
RangeEx(Addr start, Addr end)
{ return AddrRange(start, end - 1); }
inline AddrRange
RangeIn(Addr start, Addr end)
{ return AddrRange(start, end); }
inline AddrRange
RangeIn(Addr start, Addr end)
{ return AddrRange(start, end + 1); }
inline AddrRange
RangeSize(Addr start, Addr size)
{ return AddrRange(start, start + size - 1); }
{ return AddrRange(start, start + size); }
#endif // __BASE_ADDR_RANGE_HH__

1161
src/base/addr_range.test.cc
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File diff suppressed because it is too large Load Diff

20
src/dev/arm/gic_v2.cc
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@@ -51,16 +51,16 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
const AddrRange GicV2::GICD_IGROUPR (0x080, 0x0ff);
const AddrRange GicV2::GICD_ISENABLER (0x100, 0x17f);
const AddrRange GicV2::GICD_ICENABLER (0x180, 0x1ff);
const AddrRange GicV2::GICD_ISPENDR (0x200, 0x27f);
const AddrRange GicV2::GICD_ICPENDR (0x280, 0x2ff);
const AddrRange GicV2::GICD_ISACTIVER (0x300, 0x37f);
const AddrRange GicV2::GICD_ICACTIVER (0x380, 0x3ff);
const AddrRange GicV2::GICD_IPRIORITYR(0x400, 0x7ff);
const AddrRange GicV2::GICD_ITARGETSR (0x800, 0xbff);
const AddrRange GicV2::GICD_ICFGR (0xc00, 0xcff);
const AddrRange GicV2::GICD_IGROUPR (0x080, 0x100);
const AddrRange GicV2::GICD_ISENABLER (0x100, 0x180);
const AddrRange GicV2::GICD_ICENABLER (0x180, 0x200);
const AddrRange GicV2::GICD_ISPENDR (0x200, 0x280);
const AddrRange GicV2::GICD_ICPENDR (0x280, 0x300);
const AddrRange GicV2::GICD_ISACTIVER (0x300, 0x380);
const AddrRange GicV2::GICD_ICACTIVER (0x380, 0x400);
const AddrRange GicV2::GICD_IPRIORITYR(0x400, 0x800);
const AddrRange GicV2::GICD_ITARGETSR (0x800, 0xc00);
const AddrRange GicV2::GICD_ICFGR (0xc00, 0xd00);
GicV2::GicV2(const Params *p)
: BaseGic(p),

28
src/dev/arm/gic_v3_distributor.cc
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@@ -50,20 +50,20 @@
#include "dev/arm/gic_v3_cpu_interface.hh"
#include "dev/arm/gic_v3_redistributor.hh"
const AddrRange Gicv3Distributor::GICD_IGROUPR (0x0080, 0x00ff);
const AddrRange Gicv3Distributor::GICD_ISENABLER (0x0100, 0x017f);
const AddrRange Gicv3Distributor::GICD_ICENABLER (0x0180, 0x01ff);
const AddrRange Gicv3Distributor::GICD_ISPENDR (0x0200, 0x027f);
const AddrRange Gicv3Distributor::GICD_ICPENDR (0x0280, 0x02ff);
const AddrRange Gicv3Distributor::GICD_ISACTIVER (0x0300, 0x037f);
const AddrRange Gicv3Distributor::GICD_ICACTIVER (0x0380, 0x03ff);
const AddrRange Gicv3Distributor::GICD_IPRIORITYR(0x0400, 0x07ff);
const AddrRange Gicv3Distributor::GICD_ITARGETSR (0x0800, 0x08ff);
const AddrRange Gicv3Distributor::GICD_ICFGR (0x0c00, 0x0cff);
const AddrRange Gicv3Distributor::GICD_IGRPMODR (0x0d00, 0x0d7f);
const AddrRange Gicv3Distributor::GICD_NSACR (0x0e00, 0x0eff);
const AddrRange Gicv3Distributor::GICD_CPENDSGIR (0x0f10, 0x0f1f);
const AddrRange Gicv3Distributor::GICD_SPENDSGIR (0x0f20, 0x0f2f);
const AddrRange Gicv3Distributor::GICD_IGROUPR (0x0080, 0x0100);
const AddrRange Gicv3Distributor::GICD_ISENABLER (0x0100, 0x0180);
const AddrRange Gicv3Distributor::GICD_ICENABLER (0x0180, 0x0200);
const AddrRange Gicv3Distributor::GICD_ISPENDR (0x0200, 0x0280);
const AddrRange Gicv3Distributor::GICD_ICPENDR (0x0280, 0x0300);
const AddrRange Gicv3Distributor::GICD_ISACTIVER (0x0300, 0x0380);
const AddrRange Gicv3Distributor::GICD_ICACTIVER (0x0380, 0x0400);
const AddrRange Gicv3Distributor::GICD_IPRIORITYR(0x0400, 0x0800);
const AddrRange Gicv3Distributor::GICD_ITARGETSR (0x0800, 0x0900);
const AddrRange Gicv3Distributor::GICD_ICFGR (0x0c00, 0x0d00);
const AddrRange Gicv3Distributor::GICD_IGRPMODR (0x0d00, 0x0d80);
const AddrRange Gicv3Distributor::GICD_NSACR (0x0e00, 0x0f00);
const AddrRange Gicv3Distributor::GICD_CPENDSGIR (0x0f10, 0x0f20);
const AddrRange Gicv3Distributor::GICD_SPENDSGIR (0x0f20, 0x0f30);
const AddrRange Gicv3Distributor::GICD_IROUTER (0x6000, 0x7fe0);
Gicv3Distributor::Gicv3Distributor(Gicv3 * gic, uint32_t it_lines)

2
src/dev/arm/gic_v3_its.cc
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@@ -50,7 +50,7 @@
#define COMMAND(x, method) { x, DispatchEntry(#x, method) }
const AddrRange Gicv3Its::GITS_BASER(0x0100, 0x0138);
const AddrRange Gicv3Its::GITS_BASER(0x0100, 0x0140);
const uint32_t Gicv3Its::CTLR_QUIESCENT = 0x80000000;

2
src/dev/arm/gic_v3_redistributor.cc
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@@ -49,7 +49,7 @@
#include "mem/fs_translating_port_proxy.hh"
const AddrRange Gicv3Redistributor::GICR_IPRIORITYR(SGI_base + 0x0400,
SGI_base + 0x041f);
SGI_base + 0x0420);
Gicv3Redistributor::Gicv3Redistributor(Gicv3 * gic, uint32_t cpu_id)
: gic(gic),

6
src/python/m5/params.py
View File

@@ -768,7 +768,7 @@ class AddrRange(ParamValue):
if 'end' in kwargs:
self.end = Addr(kwargs.pop('end'))
elif 'size' in kwargs:
self.end = self.start + Addr(kwargs.pop('size')) - 1
self.end = self.start + Addr(kwargs.pop('size'))
else:
raise TypeError("Either end or size must be specified")
@@ -810,7 +810,7 @@ class AddrRange(ParamValue):
self.end = Addr(args[0][1])
else:
self.start = Addr(0)
self.end = Addr(args[0]) - 1
self.end = Addr(args[0])
elif len(args) == 2:
self.start = Addr(args[0])
@@ -830,7 +830,7 @@ class AddrRange(ParamValue):
def size(self):
# Divide the size by the size of the interleaving slice
return (long(self.end) - long(self.start) + 1) >> self.intlvBits
return (long(self.end) - long(self.start)) >> self.intlvBits
@classmethod
def cxx_predecls(cls, code):

2
src/sim/system.cc
View File

@@ -408,7 +408,7 @@ System::allocPhysPages(int npages)
Addr next_return_addr = pagePtr << PageShift;
AddrRange m5opRange(0xffff0000, 0xffffffff);
AddrRange m5opRange(0xffff0000, 0x100000000);
if (m5opRange.contains(next_return_addr)) {
warn("Reached m5ops MMIO region\n");
return_addr = 0xffffffff;